Abstract: An interrupt control device between clock domains is provided. An interrupt sharing logic is configured to receive one or more original interrupt signals and generate a combined interrupt signal. An interrupt processing logic is configured to output a processed interrupt signal to a processor according to the combined interrupt signal, so that the processor executes an interrupt service routine. When the interrupt service routine is executed, the processed interrupt signal changes to be disabled; before the interrupt service routine is completed, the processor outputs an interrupt clear signal to change the respective interrupt signal to be negated. After the interrupt processing logic detects that interrupt signal has been cleared successfully, the interrupt processing logic will generate the processed interrupt signal according to the combined interrupt signal again.

Abstract: A memory device includes a memory with a plurality of memory blocks and a first storage circuit to store a first data table and a first refresh value, and a memory controller with a second storage circuit to store a second data table and a second refresh value. When the memory controller meets a refresh request, the memory controller reads the second refresh value and compares the corresponding access address to the corresponding bit in the second data table to determine whether valid data are stored in a specific memory block of the memory. The memory controller sends a valid-data refresh command to the memory when valid data are stored in the specific memory block, but sends an invalid-data refresh command to the memory when invalid data are stored in the specific memory block.

Abstract: A memory device includes a memory with a plurality of memory blocks and a first storage circuit to store a first data table and a first refresh value, and a memory controller with a second storage circuit to store a second data table and a second refresh value. When the memory controller meets a refresh request, the memory controller reads the second refresh value and compares the corresponding access address to the corresponding bit in the second data table to determine whether valid data are stored in a specific memory block of the memory. The memory controller sends a valid-data refresh command to the memory when valid data are stored in the specific memory block, but sends an invalid-data refresh command to the memory when invalid data are stored in the specific memory block.

Abstract: A memory controller accessing a memory including a plurality of blocks is provided. The memory controller includes a storage circuit and a control circuit. The storage circuit stores a refresh value and a data table. The data table has a plurality of bits. Each bit indicates whether a corresponding block has valid data. The control circuit selects a specific block according to the refresh value and determines whether the specific block stores valid data according to the data table. When the specific block stores valid data, the control circuit accesses the memory after a first waiting time. When the specific block does not store any data or stores invalid data, the control circuit accesses the memory after a second waiting time. The second waiting time is shorter than the first waiting time.

Abstract: A memory control circuit, coupled to a multi-channel memory, includes a plurality of channel controllers coupled to respective channel memories of the multi-channel memory, and a built-in self-test (BIST) circuit. The BIST circuit includes a BIST controller and a plurality of command index registers which store respective command indexes related to the channel controllers. The BIST controller receives notification from at least two channel controllers of the channel controllers, which indicates that the at least two channel controllers complete respective current test commands. When the BIST controller arbitrates, the BIST controller selects at least a channel controller from the at least two channel controllers which send the notification, and sends respective next test command(s) to the selected at least one channel controller based on the respective command index(es) of the selected at least one channel controller.

Abstract: A memory controller accessing a memory including a plurality of blocks is provided. The memory controller includes a storage circuit and a control circuit. The storage circuit stores a refresh value and a data table. The data table has a plurality of bits. Each bit indicates whether a corresponding block has valid data. The control circuit selects a specific block according to the refresh value and determines whether the specific block stores valid data according to the data table. When the specific block stores valid data, the control circuit accesses the memory after a first waiting time. When the specific block does not store any data or stores invalid data, the control circuit accesses the memory after a second waiting time. The second waiting time is shorter than the first waiting time.

Abstract: A memory control circuit, coupled to a multi-channel memory, includes a plurality of channel controllers coupled to respective channel memories of the multi-channel memory, and a built-in self-test (BIST) circuit. The BIST circuit includes a BIST controller and a plurality of command index registers which store respective command indexes related to the channel controllers. The BIST controller receives notification from at least two channel controllers of the channel controllers, which indicates that the at least two channel controllers complete respective current test commands. When the BIST controller arbitrates, the BIST controller selects at least a channel controller from the at least two channel controllers which send the notification, and sends respective next test command(s) to the selected at least one channel controller based on the respective command index(es) of the selected at least one channel controller.

Abstract: The present invention relates to a method and apparatus universal serial bus (USB) physical layer. An UTM interface control logic receives a transmit data packet of USB 2.0 transceiver macrocell interface (UTMI). A transmit first-in first-out (FIFO) unit receives the transmit data packet output from the UTM interface control logic. A transmit unit receives the transmit data packet output from the transmit FIFO. An analog front-end (AFE) receives the transmitted data packet output of the transmit unit. A receive unit receives a receive data packet output from the AFE. A receive FIFO receives the receive data packet output from the receive unit and connected to the UTM interface control logic, whereby the receive data packet is output to the USB 2.0 transceiver macrocell interface.