Abstract: A method is provided for forming buried source line in semiconductor devices. It is known in the art to form buried contacts on the surface of a semiconductor substrate. The present invention discloses a method of fabricating a semiconductor device, particularly a memory cell, having both the source region and the source line buried within the substrate. The source line is formed in a trench in the substrate over the source region. The trench walls are augmented with voltage anti-punch-through protection. The trench also provides the attendant advantages of extended sidewall area, smaller sheet resistance, and yet smaller cell area, therefore, smaller chip size, and faster access time as claimed in the embodiments of this invention. The buried source disclosed here is integrated with source line which is also buried within the substrate.

Abstract: A low inductance power connector for reducing inductance in an electrical conductor is provided. An interface connector connects circuit boards together while reducing inductance and increasing current carrying capacity. The connector for connecting circuit boards comprises a first contact having a body, a first mating portion and a second mating portion, and a second contact having a body, a third mating portion and a fourth mating portion. The first and second mating portions are substantially parallel and disposed on opposite sides of the body of the first contact, and the third and fourth mating portions are substantially parallel and disposed on opposite sides of the body of the second contact.

Abstract: A method of trench polishing. A semiconductor substrate is provided. A photo-mask with a pattern is provided. The method of fabricating the photo-mask further comprising providing an original pattern which comprises a plurality of active regions with individual size. The original pattern is enlarged outwards to connect and merge some of the active regions. The active regions is diminished inwards until some small active regions eliminate, the diminished line width being denoted as B. A reverse treatment is performed to obtain a reverse pattern. The reverse pattern is enlarged with a line width C. The reverse pattern is combined with the original pattern. The substrate is patterned with the photo-mask with the combined pattern. An insulation layer is formed on the substrate. The insulation layer is polished.

Abstract: A method is provided for forming buried source line in semiconductor devices. It is known in the art to form buried contacts on the surface of a semiconductor substrate. The present invention discloses a method of fabricating a semiconductor device, particularly a memory cell, having both the source region and the source line buried within the substrate. The source line is formed in a trench in the substrate over the source region. The trench walls are augmented with voltage anti-punch-through protection. The trench also provides the attendant advantages of extended sidewall area, smaller sheet resistance, and yet smaller cell area, therefore, smaller chip size, and faster access time as claimed in the embodiments of this invention. The buried source disclosed here is integrated with source line which is also buried within the substrate.

Abstract: A method is provided for forming buried source line in semiconductor devices. It is known in the art to form buried contacts on the surface of a semiconductor substrate. The present invention discloses a method of fabricating a semiconductor device, particularly a memory cell, having both the source region and the source line buried within the substrate. The source line is formed in a trench in the substrate over the source region. The trench walls are augmented with voltage anti-punch-through protection. The trench also provides the attendant advantages of extended sidewall area, smaller sheet resistance, and yet smaller cell area, therefore, smaller chip size, and faster access time as claimed in the embodiments of this invention. The buried source disclosed here is integrated with source line which is also buried within the substrate.

Abstract: A method for forming a shallow trench isolation (STI) structure adds an etching back process to a conventional method which only uses a chemical mechanical process (CMP) process to accomplish the STI structure. In the method of the invention, the CMP process preliminarily planarizes a substrate to remove an insulation layer above the trench and uses the etching back process to accomplish the STI structure.

Abstract: A method for fabricating an embedded DRAM. A substrate having a memory circuit region and a logic circuit region is provided. A first gate, a first source/drain region and a second source/drain region are formed in the memory circuit region. A second gate and a third source/drain region are formed in the logic circuit region. A first dielectric layer is formed over the substrate. In the first dielectric layer, a first contact hole is formed to expose the first source/drain region and a second contact hole is formed to expose the second gate and the third source/drain region. A bit line is formed to electrically couple with the first source/drain region through the first contact hole. A local interconnect is formed to electrically couple with the second gate and the third source/drain region through the second contact hole. A second dielectric layer is formed over the substrate.

Abstract: A method is provided for forming a split-gate flash memory cell having reduced size, partially buried source line, increased source coupling ratio, improved programmability, and overall enhanced performance. A split-gate cell is also provided with reduced size and improved performance. The source line is formed in a trench in the substrate over the source region. The trench walls provide increased source coupling and the absence of gate bird's beak with the trench together shrink the cell size. Programmability is also enhanced through more favorable hot electron injection though intergate oxide between the floating gate and the control gate.

Abstract: A method of manufacturing a complementary metal-oxide-semiconductor that utilizes a slight change in the patterned photoresist layer for forming the lightly doped drain structure of an NMOS and the halo implantation region during CMOS fabrication. By forming a photoresist layer that exposes the p-well region where a well pickup structure is to be formed, the distance between the photoresist layer and the gate is increased, thereby eliminating the restrictions imposed upon the tilt angle in a halo implantation. Later, the lightly doped n-type impurities in the well pickup region can be compensated for by the p-type impurity implantation when the PMOS source/drain regions are formed. Hence, the lightly doped n-type well pickup region can be reverted to a p-type impurity doped region.

Abstract: A modular jack assembly including an insulative housing which has a first element a first and a second longitudinal wall positioned in spaced parallel relation and a first pair of traverse walls interposed between said first and second longitudinal walls to form a first plug receiving port. There is also a second element which has a third and fourth longitudinal wall and a second pair of transverse walls are interposed between said third and further longitudinal walls to form a forward second plug receiving port. A releasable latch fixes the third longitudinal means of the second element in superimposed abutting relation on the second longitudinal wall of the first element. A first insulative insert having base and upper sides and rear end terminal ends and is positioned such that its terminal end extends into the first plug receiving port. A second insulative insert having base and upper sides and rear and terminal ends and is positioned so that its terminal end extends into the second plug receiving.

Abstract: A method is provided for forming a split-gate flash memory cell having reduced size, partially buried source line, increased source coupling ratio, improved programmability, and overall enhanced performance. A split-gate cell is also provided with reduced size and improved performance. The source line is formed in a trench in the substrate over the source region. The trench walls provide increased source coupling and the absence of gate bird's beak with the trench together shrink the cell size. Programmability is also enhanced through more favorable hot electron injection though intergate oxide between the floating gate and the control gate.

Abstract: A method was achieved for making FET stacked gate electrode structures with improved sidewall profiles. These more vertical sidewalls improve the control tolerance of the gate electrode length (L.sub.eff) and improve the shape of the sidewall spacers for making more reliable metal contacts to the self-aligned source/drain contact areas. The method uses a stacked gate electrode layer having a TEOS oxide and a hard mask of silicon nitride on the gate electrode polysilicon layer. During patterning of the stacked gate electrode structure using a photoresist mask, the hard mask minimizes the buildup of a polymer on the TEOS oxide sidewall. This polymer would otherwise act as a masking material resulting in an abrupt step at the TEOS oxide/polysilicon interface when the polysilicon etch is completed. This results in improved gate electrode line length tolerance and much improved sidewall spacers that minimize electrical shorts between the metal source/drain contacts and the polysilicon gate electrodes.

Abstract: A semiconductor fabrication process, allowing integration of MOSFET devices, and capacitor structures, on a single semiconductor chip, has been developed. The process integration features the use of a MOSFET device, fabricated using a self-aligned contact structure, allowing a reduction in the source and drain area needed for contact. Silicon nitride spacers, used on the sides of the polysilicon gate electrode, protect the polysilicon gate structure, during the opening of a self-aligned contact hole.

Abstract: A semiconductor fabrication process, allowing integration of MOSFET devices, and capacitor structures, on a single semiconductor chip, has been developed. The process integration features the use of a MOSFET device, fabricated using a self-aligned contact structure, allowing a reduction in the source and drain area needed for contact. Silicon nitride spacers, used on the sides of the polysilicon gate electrode, protect the polysilicon gate structure, during the opening of a self-aligned contact hole. A self-aligned contact opening, to a source and drain region of a MOSFET device, as well as a capacitor contact opening, to a capacitor structure, are formed using wet-dry etching combinations. These etching combinations result in openings exhibiting sloped profiles, allowing for the attainment of reliable metal coverage, even with the use of sputtered metal depositions.

Abstract: Configurations of modular jacks adapted to be mounted on a printed circuit having a plurality of recesses located close to terminal slots at both sides to rectify dimensional variation caused by plastic shrinkage, having terminal slots constructed by two V-shape protrusions at their neck area so that the round terminal part is more precisely positioned in the housing, having a flux trap provided at a contact area between the plastic housing and a contact pin to eliminate the wicking of the flux, and having a socket.

Abstract: Disclosed is a filtered modular jack assembly having an outer insulative housing with open front and end sides. A ferrite element with vertical conductive wires is positioned adjacent the rear end, and a elongated insulative insert is superimposed over the ferrite element. The insulative insert is fixed to the housing, and the conductive wire extend vertically from the ferrite element over the upper side of the insert to its terminal end and then bend downwardly and rearwardly to rest on the top surface of an interior medial wall in the housing. A method of assembling a jack with a noise filtering capability is also disclosed.