Abstract: An apparatus includes an arbiter circuit and a translation circuit. The arbiter circuit may be configured to generate a first address signal in a virtual memory space by arbitrating among a plurality of clients to access a physical memory space. The clients may be classified as either privileged clients or non-privileged clients. The physical memory space may comprise at least one secure space. The translation circuit may be configured to generate a second address signal by translating a page in the virtual memory space into the physical memory space based on the first address signal. The page may corresponds to a particular one of the clients that won the arbitration. The page may be translated (a) into the secure space if the particular client is one of the privileged clients and (b) outside the secure space otherwise.

Abstract: An arbiter circuit and a translation circuit. The arbiter circuit may be configured to generate a first address signal in a virtual memory space by arbitrating among a plurality of clients to access a physical memory space. The clients may be classified as either privileged clients or non-privileged clients. The physical memory space may comprise at least one secure space. The secure space may be used to protect data of the privileged clients from being accessed by the non-privileged clients. The translation circuit may be configured to generate a second address signal by translating a page in the virtual memory space into the physical memory space. The page may correspond to a particular one of the clients that won the arbitration. The page may translate into the secure space if the particular client is one of the privileged clients. The page may also translate outside the secure space if the particular client is one of the non-privileged clients.

Abstract: An apparatus comprising an arbiter circuit, a translation circuit and a controller circuit. The arbiter circuit may be configured to generate one or more first control signals and a data write signal in response to an input signal and a read data signal. The translation circuit may be configured to generate a one or more second control signals in response to the one or more first control signals and the write address signal. The controller circuit may be configured to generate an address signal in response to the one or more second control signals.

Abstract: An apparatus comprising an arbiter circuit, a translation circuit and a controller circuit. The arbiter circuit may be configured to generate one or more first control signals and a data write signal in response to an input signal and a read data signal. The translation circuit may be configured to generate a one or more second control signals in response to the one or more first control signals and the write address signal. The controller circuit may be configured to generate an address signal in response to the one or more second control signals.

Abstract: An apparatus comprising an arbiter circuit, a translation circuit and a controller circuit. The arbiter circuit may be configured to generate one or more first control signals and a data write signal in response to an input signal and a read data signal. The translation circuit may be configured to generate a one or more second control signals in response to the one or more first control signals and the write address signal. The controller circuit may be configured to generate an address signal in response to the one or more second control signals.

Abstract: An apparatus and method for mapping memory addresses to reduce or avoid conflicting memory accesses in memory systems such as cache memories is described in connection with a multithreaded multiprocessor chip. A CMT processor reduces the probability of hot-spots in cache operations by hashing certain bits of a physical cache address to form a hashed cache address. By using exclusive OR functionality to hash the index bits, an efficient address transformation is achieved for indexing into an L2 cache memory.

Abstract: Method and apparatus for preserving program context when causing execution of a probe routine from a target routine of an executable computer program code. Executable code for the probe routine is created such that the probe routine does not reference a first set of registers that are usable by the target routine. A modified version of the target routine is created to cause execution of the probe routine. The modified version of the target routine is performed instead of the original version when the target routine is called during program execution. A second set of registers on the processor register stack is allocated when the probe routine is invoked. The second set of registers is not manipulated by the probe routine so as to avoid changing contents of registers of the register stack that are used by the target routine.

Abstract: Method and apparatus for instrumentation of an executable computer program that includes a predicated branch-call instruction followed by a call-shadow instruction. The predicated branch-call instruction and the call-shadow instruction is stored in a first bundle of instructions, which is followed by a second bundle. The predicated branch-call instruction is changed to a predicated branch instruction that targets a fifth bundle of instructions, and the predicate of the predicated branch instruction is the same as the predicate of the predicated branch-call instruction. Third, fourth, and fifth bundles are created to preserve program semantics. The third bundle is inserted following the first bundle and includes the call-shadow instruction. The fourth bundle is inserted following the third bundle and includes a branch instruction that targets the second bundle.

Abstract: Techniques are disclosed for preserving first content in a first register. In one embodiment, the first register is a general register, a second register is a UNaT register, and each general register is associated with a NaT bit. To preserve the content of the UNaT register while saving the content of a general register and its associated NaT bit, the content of the general register is saved to a floating-point register, and the NaT bit associated with the general register is also saved. If the NaT bit is set, then only the NaT bit is restored. Conversely, if the NaT bit is not set, then both the content of the general register and the NaT bit are restored.

Abstract: Method and apparatus for preserving program context when causing execution of a probe routine from a target routine of an executable computer program code. Executable code for the probe routine is created such that the probe routine does not reference a first set of registers that are usable by the target routine. A modified version of the target routine is created to cause execution of the probe routine. The modified version of the target routine is performed instead of the original version when the target routine is called during program execution. A second set of registers on the processor register stack is allocated when the probe routine is invoked. The second set of registers is not manipulated by the probe routine so as to avoid changing contents of registers of the register stack that are used by the target routine.

Abstract: Method and apparatus for instrumentation of an executable computer program that includes a predicated branch-call instruction followed by a call-shadow instruction. The predicated branch-call instruction and the call-shadow instruction is stored in a first bundle of instructions, which is followed by a second bundle. The predicated branch-call instruction is changed to a predicated branch instruction that targets a fifth bundle of instructions, and the predicate of the predicated branch instruction is the same as the predicate of the predicated branch-call instruction. Third, fourth, and fifth bundles are created to preserve program semantics. The third bundle is inserted following the first bundle and includes the call-shadow instruction. The fourth bundle is inserted following the third bundle and includes a branch instruction that targets the second bundle.

Abstract: Techniques are disclosed for preserving first content in a first register while maintaining second content in a second register wherein saving the first content to memory changes the second content in the second register. In one embodiment, the first register is a general register, the second register is a UNaT register, and each general register is associated with a NaT bit. To preserve the content of the UNaT register while saving the content of a general register and its associated NaT bit so that the general register may be used in programming code modification, in one embodiment, the content of the general register is saved to a floating-point register. After the general register has been used, the content of the general register saved in the floating-point register is restored to the general register. In one embodiment, when the content of a general register is saved to the floating-point register, the NaT bit associated with the general register is also saved.

Abstract: Techniques are disclosed for allocating an N number of registers for use in conjunction with programming code modification, which is usually implemented in code instrumentation. During code instrumentation, new code or “probe” code is added to the block, and, consequently, the original code is changed and/or relocated, resulting in a modified block. In one embodiment, a block of code is associated with an “alloc” statement that uses parameters based on which the programming system allocates the stacked registers for use in that block. Further, the parameters of an alloc statement include an input parameter identifying a number I of input registers, a local parameter identifying a number L of local registers, and an output parameter identifying a number O of output registers. Consequently, the I number of input registers, the L number of local registers, and the O number of output registers are to be allocated.