Abstract: Embodiments disclosed herein include a method of etching a 3D structure. In an embodiment, the method comprises providing the 3D structure in a microwave plasma chamber. In an embodiment, the 3D structure comprises a substrate, and alternating layers of silicon oxide and silicon nitride over the substrate. In an embodiment, the method further comprises flowing a first gas into the microwave plasma chamber, where the first gas comprises sulfur and fluorine. In an embodiment, the method comprises flowing a second gas into the microwave plasma chamber, where the second gas comprises an inert gas. In an embodiment, the method further comprises striking a plasma in the microwave plasma chamber, and etching the silicon nitride, where an etching selectivity of silicon nitride to silicon oxide is 50:1 or greater.

Abstract: The present disclosure generally relates to methods for processing of substrates, and more particularly relates to methods for forming a metal gapfill. In one implementation, the method includes forming a metal gapfill in an opening using a multi-step process. The multi-step process includes forming a first portion of the metal gapfill, performing a sputter process to form one or more layers on one or more side walls, and growing a second portion of the metal gapfill to fill the opening with the metal gapfill. The metal gapfill formed by the multi-step process is seamless, and the one or more layers formed on the one or more side walls seal any gaps or defects between the metal gapfill and the side walls. As a result, fluids utilized in subsequent processes do not diffuse through the metal gapfill.

Abstract: Embodiments of methods for depositing material in features of a substrate have been provided herein. In some embodiments, a method for depositing material in a feature of a substrate includes depositing a material in a feature of a substrate disposed in a process chamber by sputtering a target using a plasma formed from a first gas; and etching the deposited material in the process chamber using a plasma formed from a second gas, different than the first gas, to at least partially reduce overhang of the material in the feature, wherein an atomic mass of the second gas is greater than an atomic mass of the first gas.

Abstract: The present disclosure generally relates to methods for processing of substrates, and more particularly relates to methods for forming a metal gapfill. In one implementation, the method includes forming a metal gapfill in an opening using a multi-step process. The multi-step process includes forming a first portion of the metal gapfill, performing a sputter process to form one or more layers on one or more side walls, and growing a second portion of the metal gapfill to fill the opening with the metal gapfill. The metal gapfill formed by the multi-step process is seamless, and the one or more layers formed on the one or more side walls seal any gaps or defects between the metal gapfill and the side walls. As a result, fluids utilized in subsequent processes do not diffuse through the metal gapfill.

Abstract: Methods of forming a contact line comprising cleaning the surface of a cobalt film in a trench and forming a protective layer on the surface of the cobalt, the protective layer comprising one or more of a silicide or germide. Semiconductor devices with the contact lines are also disclosed.

Abstract: Implementations of the present disclosure generally relate to methods for epitaxial growth of a silicon material on an epitaxial film. In one implementation, the method includes forming an epitaxial film over a semiconductor fin, wherein the epitaxial film includes a top surface having a first facet and a second facet, and forming an epitaxial layer on at least the top surface of the epitaxial film by alternatingly exposing the top surface to a first precursor gas comprising one or more silanes and a second precursor gas comprising one or more chlorinated silanes at a temperature of about 375° C. to about 450° C. and a chamber pressure of about 5 Torr to about 20 Torr.

Abstract: Implementations of the present disclosure generally relate to methods for epitaxial growth of a silicon material on an epitaxial film. In one implementation, the method includes forming an epitaxial film over a semiconductor fin, wherein the epitaxial film includes a top surface having a first facet and a second facet, and forming an epitaxial layer on at least the top surface of the epitaxial film by alternatingly exposing the top surface to a first precursor gas comprising one or more silanes and a second precursor gas comprising one or more chlorinated silanes at a temperature of about 375° C. to about 450° C. and a chamber pressure of about 5 Torr to about 20 Torr.

Abstract: Implementations of the present disclosure generally relate to methods for epitaxial growth of a silicon material on an epitaxial film. In one implementation, the method includes forming an epitaxial film over a semiconductor fin, wherein the epitaxial film includes a top surface having a first facet and a second facet, and forming an epitaxial layer on at least the top surface of the epitaxial film by alternatingly exposing the top surface to a first precursor gas comprising one or more silanes and a second precursor gas comprising one or more chlorinated silanes at a temperature of about 375° C. to about 450° C. and a chamber pressure of about 5 Torr to about 20 Torr.

Abstract: Implementations of the present disclosure generally relate to methods for epitaxial growth of a silicon material on an epitaxial film. In one implementation, the method includes forming an epitaxial film over a semiconductor fin, wherein the epitaxial film includes a top surface having a first facet and a second facet, and forming an epitaxial layer on at least the top surface of the epitaxial film by alternatingly exposing the top surface to a first precursor gas comprising one or more silanes and a second precursor gas comprising one or more chlorinated silanes at a temperature of about 375° C. to about 450° C. and a chamber pressure of about 5 Torr to about 20 Torr.

Abstract: Embodiments of methods for depositing material in features of a substrate have been provided herein. In some embodiments, a method for depositing material in a feature of a substrate includes depositing a material in a feature of a substrate disposed in a process chamber by sputtering a target using a plasma formed from a first gas; and etching the deposited material in the process chamber using a plasma formed from a second gas, different than the first gas, to at least partially reduce overhang of the material in the feature, wherein an atomic mass of the second gas is greater than an atomic mass of the first gas.

Abstract: Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. One embodiment provides a method provides a method for processing a substrate comprising forming a seed layer over a substrate having trench or via structures formed therein, coating a portion of the seed layer with an organic passivation film, and immersing the trench or via structures in a plating solution to deposit a conductive material over the seed layer not covered by the organic passivation film.

Abstract: Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. One embodiment provides a method provides a method for processing a substrate comprising forming a seed layer over a substrate having trench or via structures formed therein, coating a portion of the seed layer with an organic passivation film, and immersing the trench or via structures in a plating solution to deposit a conductive material over the seed layer not covered by the organic passivation film.

Abstract: A method and resultant produce of forming barrier layer based on ruthenium tantalum in a via or other vertical interconnect structure through a dielectric layer in a multi-level metallization. The RuTa layer in a RuTa/RuTaN bilayer, which may form discontinuous islands, is actively oxidized, preferably in an oxygen plasma, to thereby bridge the gaps between the islands. Alternatively, ruthenium tantalum oxide is reactive sputtered onto the RuTaN or directly onto the underlying dielectric by plasma sputtering a RuTa target in the presence of oxygen.

Abstract: Methods for forming a metal interconnection structure in thin-film transistor applications are provided in the present invention. In one embodiment, the method may include providing a substrate into a processing chamber, supplying a first gas mixture into the chamber to deposit a metal layer on the substrate, and supplying a second gas mixture into the chamber to deposit a barrier layer on the metal layer. In another embodiment, a metal interconnection structure may include a substrate, a first barrier layer disposed on the substrate, a metal layer disposed on the substrate in a processing chamber, a second barrier layer disposed on the metal layer formed in the processing chamber a second barrier layer disposed on the metal layer formed in the processing chamber, wherein the first barrier layer, the metal layer and the second barrier layer are configured to form a metal interconnection structure for TFT devices.

Abstract: A method and resultant produce of forming barrier layer based on ruthenium tantalum in a via or other vertical interconnect structure through a dielectric layer in a multi-level metallization. The RuTa layer in a RuTa/RuTaN bilayer, which may form discontinuous islands, is actively oxidized, preferably in an oxygen plasma, to thereby bridge the gaps between the islands. Alternatively, ruthenium tantalum oxide is reactive sputtered onto the RuTaN or directly onto the underlying dielectric by plasma sputtering a RuTa target in the presence of oxygen.