Patents by Inventor Jennifer A. Hester

Jennifer A. Hester has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7211894
    Abstract: According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, a dielectric disposed between the first conductive plane and the second conductive plane, a third conductive plane electrically coupled to the second terminal and not electrically coupled to the first terminal, and a second dielectric disposed between the second conductive plane and the third conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: May 1, 2007
    Assignee: Intel Corporation
    Inventors: Jennifer A. Hester, Yuan-Liang Li, Michael M. Desmith, David G. Figueroa, Dong Zhong
  • Publication number: 20060138639
    Abstract: According to some embodiments, an apparatus includes a first conductive pad, a first conductive plane, first dielectric material disposed between the first conductive plane and the first conductive pad, a second conductive plane, second dielectric material disposed between the first conductive plane and the second conductive plane, and a first conductive network.
    Type: Application
    Filed: December 28, 2004
    Publication date: June 29, 2006
    Inventors: David Figueroa, Jennifer Hester, Yuan-Liang Li
  • Patent number: 6992387
    Abstract: According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, and a dielectric disposed between the first conductive plane and the second conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: January 31, 2006
    Assignee: Intel Corporation
    Inventors: Jennifer A. Hester, Yuan-Liang Li, Michael M. Desmith, David G. Figueroa, Dong Zhong
  • Publication number: 20050194675
    Abstract: According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, and a dielectric disposed between the first conductive plane and the second conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.
    Type: Application
    Filed: April 12, 2005
    Publication date: September 8, 2005
    Inventors: Jennifer Hester, Yuan-Liang Li, Michael Desmith, David Figueroa, Dong Zhong
  • Patent number: 6879494
    Abstract: A circuit package has been described for routing long traces between an electronic circuit, such as a phase locked loop, and external circuit components. The traces are routed through two substrates. In each substrate, the traces are routed primarily on a layer adjacent to and between a pair ground planes located close to the traces. Degassing apertures are located to the side of the long traces to avoid interfering with the shielding provided by the grounds planes. The circuit package uses two power plated through holes and two ground plated through holes to reduce the noise on the power supply lines. The circuit package also separates the signal carrying plated through holes from the power plated through holes, which reduces noise on the long traces. Noise is further reduced on the long traces by using the ground plated through holes to shield the signal carrying plated through holes from noise generated at the power plated through holes.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: April 12, 2005
    Assignee: Intel Corporation
    Inventors: Longqiang L. Zu, Jennifer A. Hester
  • Publication number: 20040257780
    Abstract: According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, and a dielectric disposed between the first conductive plane and the second conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.
    Type: Application
    Filed: June 23, 2003
    Publication date: December 23, 2004
    Inventors: Jennifer A. Hester, Yuan-Liang Li, Michael M. Desmith, David G. Figueroa, Dong Zhong
  • Publication number: 20030206405
    Abstract: A circuit package has been described for routing long traces between an electronic circuit, such as a phase locked loop, and external circuit components. The traces are routed through two substrates. In each substrate, the traces are routed primarily on a layer adjacent to and between a pair ground planes located close to the traces. Degassing apertures are located to the side of the long traces to avoid interfering with the shielding provided by the grounds planes. The circuit package uses two power plated through holes and two ground plated through holes to reduce the noise on the power supply lines. The circuit package also separates the signal carrying plated through holes from the power plated through holes, which reduces noise on the long traces. Noise is further reduced on the long traces by using the ground plated through holes to shield the signal carrying plated through holes from noise generated at the power plated through holes.
    Type: Application
    Filed: May 27, 2003
    Publication date: November 6, 2003
    Applicant: Intel Corporation
    Inventors: Longqiang L. Zu, Jennifer A. Hester
  • Patent number: 6594153
    Abstract: A circuit package has been described for routing long traces between an electronic circuit, such as a phase locked loop, and external circuit components. The traces are routed through two substrates. In each substrate, the traces are routed primarily on a layer adjacent to and between a pair ground planes located close to the traces. Degassing apertures are located to the side of the long traces to avoid interfering with the shielding provided by the grounds planes. The circuit package uses two power plated through holes and two ground plated through holes to reduce the noise on the power supply lines. The circuit package also separates the signal carrying plated through holes from the power plated through holes, which reduces noise on the long traces. Noise is further reduced on the long traces by using the ground plated through holes to shield the signal carrying plated through holes from noise generated at the power plated through holes.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: July 15, 2003
    Assignee: Intel Corporation
    Inventors: Longqiang L. Zu, Jennifer A. Hester