Patents by Inventor Jennifer Church
Jennifer Church has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105590Abstract: Semiconductor devices and methods of making the same include a first lower device and a second lower device on a substrate. A first upper device is over the first lower device and a second upper device is over the second lower device. A first lower contact extends from a height above the first upper device and makes electrical contact with a top surface and a sidewall surface of the first lower device. A second lower contact extends from a height above the second upper device and makes electrical contact with a top surface and a sidewall surface of the second lower device. An insulating barrier is between the first lower contact and the second lower contact.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Inventors: Koichi Motoyama, Ruilong Xie, Jennifer Church, Oleg Gluschenkov
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Patent number: 11906901Abstract: Alternating copolymers having hydrocarbon-substituted terminal units and repeat units each containing two different monomer units with extreme ultraviolet (EUV)-absorbing elements are disclosed. Alternating copolymers having organic terminal units and repeat units each containing a monomer unit with an EUV-absorbing element and an organic monomer unit are also disclosed. A process of forming a polymer resist, which includes providing an alternating copolymer having repeat units with at least one EUV-absorbing monomer unit and replacing end groups of the alternating copolymer with unreactive terminal units, is disclosed as well.Type: GrantFiled: June 7, 2021Date of Patent: February 20, 2024Assignee: International Business Machines CorporationInventors: Dario Goldfarb, Ekmini Anuja De Silva, Jing Guo, Jennifer Church, Luciana Meli
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Publication number: 20230403951Abstract: A semiconductor device structure and a method for fabricating the same. The semiconductor device structure includes an embedded memory device and an electrode in contact with a top surface of the memory embedded device. A metal encapsulation layer is in contact with a top surface of the electrode and a portion of sidewalls of the electrode. The metal encapsulation layer comprises one or more materials that are chemical etch resistant and are conductive when oxidized. The method includes forming an insulating layer over a memory device and an electrode in contact with the memory device. Portions of the insulating layer are etched. The etching exposes a top surface and a portion of sidewalls of the electrode. A metal encapsulation layer is formed over and in contact with the top surface and the portion of sidewalls of the electrode.Type: ApplicationFiled: August 25, 2023Publication date: December 14, 2023Inventors: Ashim DUTTA, Ekmini Anuja DE SILVA, Jennifer CHURCH
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Publication number: 20230343593Abstract: Various embodiments herein relate to methods, apparatus, and systems that utilize a multi-layer hardmask in the context of patterning a semiconductor substrate using extreme ultraviolet photoresist. The multi-layer hardmask includes (1) an upper layer that includes a metal-containing material such as a metal oxide, a metal nitride, or a metal oxynitride, and (2) a lower layer that includes an inorganic dielectric silicon-containing material. Together, these layers of the multi-layer hardmask provide excellent etch selectivity and reduce formation of defects such as microbridges and line breaks. Certain embodiments relate to deposition of the multi-layer hardmask. Other embodiments relate to etching of the multi-layer hardmask. Some embodiments involve both deposition and etching of the multi-layer hardmask.Type: ApplicationFiled: February 23, 2021Publication date: October 26, 2023Inventors: Bhaskar NAGABHIRAVA, Phillip FRIDDLE, Ekimini Anuja DE SILVA, Jennifer CHURCH, Dominik METZLER, Nelson FELIX
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Patent number: 11778929Abstract: A semiconductor device structure and a method for fabricating the same. The semiconductor device structure includes an embedded memory device and an electrode in contact with a top surface of the memory embedded device. A metal encapsulation layer is in contact with a top surface of the electrode and a portion of sidewalls of the electrode. The metal encapsulation layer comprises one or more materials that are chemical etch resistant and are conductive when oxidized. The method includes forming an insulating layer over a memory device and an electrode in contact with the memory device. Portions of the insulating layer are etched. The etching exposes a top surface and a portion of sidewalls of the electrode. A metal encapsulation layer is formed over and in contact with the top surface and the portion of sidewalls of the electrode.Type: GrantFiled: February 27, 2019Date of Patent: October 3, 2023Assignee: International Business Machines CorporationInventors: Ashim Dutta, Ekmini Anuja De Silva, Jennifer Church
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Publication number: 20230290682Abstract: A semiconductor substrate has a metal via in the substrate, and has, on the substrate, a metal line that is less than 8 nanometers (nm) wide and at least 20 nm tall. A method for making a semiconductor structure includes forming a metal via in a substrate; forming a mandrel atop and offset from the via; depositing a metal-containing liner onto the mandrel; exposing the top of the mandrel by anisotropically etching the liner, thereby defining a separate portion of the liner at each side of the mandrel; and growing a metal line on each portion of the liner.Type: ApplicationFiled: March 9, 2022Publication date: September 14, 2023Inventors: Ashim Dutta, Ekmini Anuja De Silva, Chih-Chao Yang, Jennifer Church
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Publication number: 20230099965Abstract: Airgap isolation for back-end-of-the-line interconnect structures includes a dielectric liner formed above a top surface and opposite sidewalls of each of a plurality of metal lines on a substrate, the dielectric liner disposed above a top surface of the substrate not covered by the plurality of metal lines, portions of the dielectric liner located on the opposite sidewalls of each of the plurality of metal lines are separated by a space. A dielectric cap is disposed above an uppermost surface of portions of the dielectric liner above each of the plurality of metal lines and above the space, the dielectric cap pinches-off the space between portions of the dielectric liner located on the opposite sidewalls of each of the plurality of metal lines for providing airgaps between adjacent metal lines.Type: ApplicationFiled: September 29, 2021Publication date: March 30, 2023Inventors: Ashim Dutta, Ekmini Anuja De Silva, Praveen Joseph, Jennifer Church
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Patent number: 11543751Abstract: An exemplary semiconductor fabrication stack includes underlying layers; an organic planarization layer atop the underlying layers; a metal oxide hardmask atop the organic planarization layer and doped with both carbon and nitrogen; and an organic photoresist directly atop the doped metal oxide hardmask. In one or more embodiments, the doped metal oxide hardmask exhibits a water contact angle of greater than 80°.Type: GrantFiled: April 16, 2020Date of Patent: January 3, 2023Assignee: International Business Machines CorporationInventors: Abraham Arceo de la Pena, Jennifer Church, Nelson Felix, Ekmini Anuja De Silva
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Publication number: 20220390845Abstract: Alternating copolymers having hydrocarbon-substituted terminal units and repeat units each containing two different monomer units with extreme ultraviolet (EUV)-absorbing elements are disclosed. Alternating copolymers having organic terminal units and repeat units each containing a monomer unit with an EUV-absorbing element and an organic monomer unit are also disclosed. A process of forming a polymer resist, which includes providing an alternating copolymer having repeat units with at least one EUV-absorbing monomer unit and replacing end groups of the alternating copolymer with unreactive terminal units, is disclosed as well.Type: ApplicationFiled: June 7, 2021Publication date: December 8, 2022Inventors: Dario Goldfarb, Ekmini Anuja De Silva, Jing Guo, Jennifer Church, Luciana Meli
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Patent number: 11367617Abstract: A patterning stack and methods are provided for semiconductor processing. The method includes forming a graded hardmask, the graded hardmask including a first material and a second material with extreme ultraviolet (EUV) absorption cross sections for absorption of EUV wavelengths, the second material configured to provide adhesion to photoresist materials. The method also includes depositing a photoresist layer over the graded hardmask. The method additionally includes patterning the photoresist layer. The method further includes etching the graded hardmask. The method also includes removing the photoresist layer.Type: GrantFiled: March 10, 2021Date of Patent: June 21, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jennifer Church, Ekmini A. De Silva, Dario Goldfarb
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Patent number: 11307496Abstract: A metal brush layer is provided. The metal brush layer includes a polymer backbone including at least one grafting unit, G, attached to the polymer backbone, and a plurality of metal-containing moieties, M, attached to the polymer backbone.Type: GrantFiled: November 19, 2019Date of Patent: April 19, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ekmini Anuja De Silva, Jing Guo, Jennifer Church, Dario Goldfarb
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Publication number: 20220043353Abstract: A method of making an adhesion layer of an extreme ultraviolet (EUV) stack is presented. The method includes grafting an ultraviolet (UV) sensitive polymer brush on a hardmask, the polymer brush including a UV cleavable unit, depositing EUV resist over the polymer brush, exposing the EUV resist to remove the EUV resist in exposed areas by applying a developer, and flooding the exposed area with a UV light and a solvent developer to remove exposed portions of the polymer brush.Type: ApplicationFiled: October 22, 2021Publication date: February 10, 2022Inventors: Jing Guo, Bharat Kumar, Ekmini A. De Silva, Jennifer Church, Dario Goldfarb, Nelson Felix
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Patent number: 11199778Abstract: A method of making an adhesion layer of an extreme ultraviolet (EUV) stack is presented. The method includes grafting an ultraviolet (UV) sensitive polymer brush on a hardmask, the polymer brush including a UV cleavable unit, depositing EUV resist over the polymer brush, exposing the EUV resist to remove the EUV resist in exposed areas by applying a developer, and flooding the exposed area with a UV light and a solvent developer to remove exposed portions of the polymer brush.Type: GrantFiled: March 12, 2019Date of Patent: December 14, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jing Guo, Bharat Kumar, Ekmini A. De Silva, Jennifer Church, Dario Goldfarb, Nelson Felix
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Publication number: 20210325784Abstract: An exemplary semiconductor fabrication stack includes underlying layers; an organic planarization layer atop the underlying layers; a metal oxide hardmask atop the organic planarization layer and doped with both carbon and nitrogen; and an organic photoresist directly atop the doped metal oxide hardmask. In one or more embodiments, the doped metal oxide hardmask exhibits a water contact angle of greater than 80°.Type: ApplicationFiled: April 16, 2020Publication date: October 21, 2021Inventors: Abraham Arceo de la Pena, Jennifer Church, Nelson Felix, Ekmini Anuja De Silva
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Patent number: 11062946Abstract: A method for forming one or more self-aligned contacts on a semiconductor device includes applying a protective layer on an oxide surface above a source and drain of the semiconductor device. The protective layer covers a top surface of the oxide surface selective to nitride above a gate contact pillar. A sacrificial layer is applied to the nitride surface. The sacrificial layer is deposited only on the nitride surface that is selective to the oxide layer coated with the protective layer. The protective layer is removed from the oxide surface and source/drain contact holes are etched in the oxide surface to form self-aligned contacts on the semiconductor device.Type: GrantFiled: November 8, 2018Date of Patent: July 13, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ashim Dutta, Jennifer Church, Ekmini A. de Silva, Luciana M. Thompson
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Publication number: 20210202249Abstract: A patterning stack and methods are provided for semiconductor processing. The method includes forming a graded hardmask, the graded hardmask including a first material and a second material with extreme ultraviolet (EUV) absorption cross sections for absorption of EUV wavelengths, the second material configured to provide adhesion to photoresist materials. The method also includes depositing a photoresist layer over the graded hardmask. The method additionally includes patterning the photoresist layer. The method further includes etching the graded hardmask.Type: ApplicationFiled: March 10, 2021Publication date: July 1, 2021Inventors: Jennifer Church, Ekmini A. De Silva, Dario Goldfarb
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Publication number: 20210149298Abstract: A metal brush layer is provided. The metal brush layer includes a polymer backbone including at least one grafting unit, G, attached to the polymer backbone, and a plurality of metal-containing moieties, M, attached to the polymer backbone.Type: ApplicationFiled: November 19, 2019Publication date: May 20, 2021Inventors: Ekmini Anuja De Silva, Jing Guo, Jennifer Church, Dario Goldfarb
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Patent number: 10998191Abstract: A patterning stack and methods are provided for semiconductor processing. The method includes forming a graded hardmask, the graded hardmask including a first material and a second material with extreme ultraviolet (EUV) absorption cross sections for absorption of EUV wavelengths, the second material configured to provide adhesion to photoresist materials. The method also includes depositing a photoresist layer over the graded hardmask. The method additionally includes patterning the photoresist layer. The method further includes etching the graded hardmask. The method also includes removing the photoresist layer.Type: GrantFiled: November 13, 2018Date of Patent: May 4, 2021Assignee: International Business Machines CorporationInventors: Jennifer Church, Ekmini A. De Silva, Dario Goldfarb
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Patent number: 10886462Abstract: A method for selectively encapsulating embedded memory pillars in a semiconductor device includes coating a passivation layer on a first dielectric surface on a first outer dielectric layer present in the semiconductor device. The passivation layer adheres to the dielectric surface selective to metal. The method includes depositing an encapsulation layer on side and top surfaces of the embedded memory pillars. The passivation layer prevents deposition of the encapsulation layer on the first dielectric surface of the first outer layer dielectric. The method includes removing the first outer dielectric layer from horizontal subraces around the embedded memory pillar and the encapsulation layer from the top surface of the embedded memory pillars.Type: GrantFiled: November 19, 2018Date of Patent: January 5, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ashim Dutta, Ekmini Anuja de Silva, Jennifer Church, Luciana Meli Thompson
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Patent number: 10879107Abstract: A method includes forming a first insulating layer having one or more vias formed in at least a portion of the first insulating layer. The vias are filled with a first metallic material. A cap layer is deposited on a top surface of the first insulating layer and a top surface of the one or more vias and a second insulating layer is deposited on a top surface of the cap layer. One or more openings are formed in the second insulating layer and the cap layer. A self-assembled monolayer is formed on an exposed top surface of the first metallic material in the one or more vias. A barrier layer is formed on at least the exposed surface of the one or more openings. The self-assembled monolayer is removed and the one or more openings are filled with a second metallic material.Type: GrantFiled: November 5, 2018Date of Patent: December 29, 2020Assignee: International Business Machines CorporationInventors: Ashim Dutta, Ekmini Anuja De Silva, Jennifer Church, Luciana Meli Thompson