Patents by Inventor Jennifer D. Schuler
Jennifer D. Schuler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220304175Abstract: A component for an electronic device can include a pre-formed substrate comprising a first metal and an additively manufactured portion bonded to the pre-formed substrate. The additively manufactured portion can include a first portion comprising a second metal and defining a volume, the first portion having a first value of a material property, and a second portion disposed in the volume, the second portion having a second value of the material property that is different from the first value.Type: ApplicationFiled: June 6, 2022Publication date: September 22, 2022Inventors: Eric W. Hamann, Abhijeet Misra, Anthony D. Prescenzi, Brian M. Gable, Christopher D. Prest, Hoishun Li, James A. Yurko, Lee E. Hooton, Michael B. Wittenberg, Richard H. Dinh, Jennifer D. Schuler
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Patent number: 9804498Abstract: A photoresist stripping tool includes a reservoir configured to contain photoresist stripping solution and a Pb filter comprising a filter element with Tin (Sn) exterior surfaces. A semiconductor wafer fabrication system includes a semiconductor wafer attached to the photoresist stripping tool that strips photoresist from the semiconductor wafer. A photoresist stripping processes includes stripping photoresist from a leaded semiconductor wafer with photoresist stripping solution within the photoresist stripping tool, filtering Lead Pb from the photoresist stripping solution with the Pb filter, and stripping photoresist from a lead-free semiconductor wafer with the filtered photoresist stripping solution.Type: GrantFiled: June 9, 2014Date of Patent: October 31, 2017Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Harry D. Cox, Arthur G. Merryman, Jennifer D. Schuler
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Patent number: 9754823Abstract: A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.Type: GrantFiled: May 28, 2014Date of Patent: September 5, 2017Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, SÜSS MICROTEC PHOTONIC SYSTEMS INC.Inventors: Yuri M. Brovman, Brian M. Erwin, Nicholas A. Polomoff, Jennifer D. Schuler, Matthew E. Souter, Christopher L. Tessler
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Patent number: 9748135Abstract: A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.Type: GrantFiled: August 18, 2015Date of Patent: August 29, 2017Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, SUSS MICROTEC PHOTONIC SYSTEMS INC.Inventors: Yuri M. Brovman, Brian M. Erwin, Nicholas A. Polomoff, Jennifer D. Schuler, Matthew E. Souter, Christopher L. Tessler
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Patent number: 9728440Abstract: A method for processing a semiconductor wafer where an opaque layer is located on a surface of a handling wafer is used so the surface of the handling wafer may be detected through optical sensors. The opaque layer may be modified, or oriented, to allow light to pass through unobstructed.Type: GrantFiled: October 28, 2014Date of Patent: August 8, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Charles L. Arvin, Harry D. Cox, Brian M. Erwin, Jorge A. Lubguban, Eric D. Perfecto, Jennifer D. Schuler
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Patent number: 9679796Abstract: A method for processing a semiconductor wafer where an electrostatic layer is located on a surface of a handling wafer is used so the surface of the handling wafer may be handled with machinery that uses an electrostatic chuck. The electrostatic layer may be manipulated to increase or decrease the conductivity, and may be removed to allow light to pass through the handling wafer.Type: GrantFiled: October 28, 2014Date of Patent: June 13, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Charles L. Arvin, Harry D. Cox, Jorge A. Lubguban, Jennifer D. Schuler
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Publication number: 20160204028Abstract: A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.Type: ApplicationFiled: March 17, 2016Publication date: July 14, 2016Inventors: Yuri M. Brovman, Brian M. Erwin, Nicholas A. Polomoff, Jennifer D. Schuler, Matthew E. Souter, Christopher L. Tessler
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Publication number: 20160118283Abstract: A method for processing a semiconductor wafer where an electrostatic layer is located on a surface of a handling wafer is used so the surface of the handling wafer may be handled with machinery that uses an electrostatic chuck. The electrostatic layer may be manipulated to increase or decrease the conductivity, and may be removed to allow light to pass through the handling wafer.Type: ApplicationFiled: October 28, 2014Publication date: April 28, 2016Inventors: Charles L. Arvin, Harry D. Cox, Jorge A. Lubguban, Jennifer D. Schuler
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Publication number: 20160118287Abstract: A method for processing a semiconductor wafer where an opaque layer is located on a surface of a handling wafer is used so the surface of the handling wafer may be detected through optical sensors. The opaque layer may be modified, or oriented, to allow light to pass through unobstructed.Type: ApplicationFiled: October 28, 2014Publication date: April 28, 2016Inventors: Charles L. Arvin, Harry D. Cox, Brian M. Erwin, Jorge A. Lubguban, Eric D. Perfecto, Jennifer D. Schuler
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Publication number: 20150357235Abstract: A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.Type: ApplicationFiled: August 18, 2015Publication date: December 10, 2015Inventors: Yuri M. Brovman, Brian M. Erwin, Nicholas A. Polomoff, Jennifer D. Schuler, Matthew E. Souter, Christopher L. Tessler
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Publication number: 20150352476Abstract: A photoresist stripping tool includes a reservoir configured to contain photoresist stripping solution and a Pb filter comprising a filter element with Tin (Sn) exterior surfaces. A semiconductor wafer fabrication system includes a semiconductor wafer attached to the photoresist stripping tool that strips photoresist from the semiconductor wafer. A photoresist stripping processes includes stripping photoresist from a leaded semiconductor wafer with photoresist stripping solution within the photoresist stripping tool, filtering Lead Pb from the photoresist stripping solution with the Pb filter, and stripping photoresist from a lead-free semiconductor wafer with the filtered photoresist stripping solution.Type: ApplicationFiled: June 9, 2014Publication date: December 10, 2015Inventors: Charles L. Arvin, Harry D. Cox, Arthur G. Merryman, Jennifer D. Schuler
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Publication number: 20150348831Abstract: A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.Type: ApplicationFiled: May 28, 2014Publication date: December 3, 2015Applicants: International Business Machines Corporation, SUSS MicroTec Photonic Systems Inc.Inventors: Yuri M. Brovman, Brian M. Erwin, Nicholas A. Polomoff, Jennifer D. Schuler, Matthew E. Souter, Christopher L. Tessler
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Publication number: 20150348910Abstract: A structure including a stack of conformal layers on top of a dielectric layer and within an opening in the dielectric layer, the stack of layers including a first layer, a second layer, a third layer, and a fourth layer, each formed successively one on top of another with the first layer being in direct contact with the dielectric layer, and a conductive feature located directly on top of the fourth layer within the opening.Type: ApplicationFiled: August 11, 2015Publication date: December 3, 2015Inventors: Charles L. Arvin, Harry D. Cox, Brian M. Erwin, John J. Garant, Ekta Misra, Nicholas A. Polomoff, Jennifer D. Schuler
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Publication number: 20150311161Abstract: A method including forming a stack of layers on top of a dielectric layer and within an opening in the dielectric layer, the stack of layers comprising a first layer, a second layer, a third layer, and a fourth layer, each formed successively one on top of another, removing a first portion of the fourth layer outside the opening to expose a portion of the third layer, a second portion of the fourth layer remains within the opening, filling the opening with a metal by applying an electrical potential to the second layer during an electroplating technique in which the metal plates out on the fourth layer but does not plate out on the third layer, and removing portions of the first layer, the second layer, and the third layer to expose an upper surface of the dielectric layer between the opening and an adjacent opening.Type: ApplicationFiled: April 28, 2014Publication date: October 29, 2015Applicant: International Business Machines CorporationInventors: Charles L. Arvin, Harry D. Cox, Brian M. Erwin, John J. Garant, Ekta Misra, Nicholas A. Polomoff, Jennifer D. Schuler
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Patent number: 8759210Abstract: A solder structure for joining an IC chip to a package substrate, and method of forming the same are disclosed. In an embodiment, a structure is formed which includes a wafer having a plurality of solder structures disposed above the wafer. A ball limiting metallurgy (BLM) layer disposed beneath each of the solder structures, above the wafer. At least one of the plurality of solder structures has a first composition, and at least another of the plurality of solder structures has a second composition.Type: GrantFiled: July 19, 2012Date of Patent: June 24, 2014Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Wolfgang Sauter, Jennifer D. Schuler
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Patent number: 8742578Abstract: An integrated circuit (IC) chip including solder structures for connection to a package substrate, an IC chip package, and a method of forming the same are disclosed. In an embodiment, an IC chip is provided comprising a wafer having a plurality of solder structures disposed above the wafer. A ball limiting metallurgy (BLM) layer is disposed between each of the plurality of solder structures and the wafer. At least one of the plurality of solder structures has a first diameter and a first height, and at least one other solder structure has a second diameter and a second height. The differing heights and volumes of solder structures facilitate solder volume compensation for chip join improvement on the IC chip side rather than the package side.Type: GrantFiled: July 19, 2012Date of Patent: June 3, 2014Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Eric D. Perfecto, Wolfgang Sauter, Jennifer D. Schuler
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Publication number: 20140021607Abstract: An integrated circuit (IC) chip including solder structures for connection to a package substrate, an IC chip package, and a method of forming the same are disclosed. In an embodiment, an IC chip is provided comprising a wafer having a plurality of solder structures disposed above the wafer. A ball limiting metallurgy (BLM) layer is disposed between each of the plurality of solder structures and the wafer. At least one of the plurality of solder structures has a first diameter and a first height, and at least one other solder structure has a second diameter and a second height. The differing heights and volumes of solder structures facilitate solder volume compensation for chip join improvement on the IC chip side rather than the package side.Type: ApplicationFiled: July 19, 2012Publication date: January 23, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles L. Arvin, Eric D. Perfecto, Wolfgang Sauter, Jennifer D. Schuler
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Publication number: 20140021606Abstract: A solder structure for joining an IC chip to a package substrate, and method of forming the same are disclosed. In an embodiment, a structure is formed which includes a wafer having a plurality of solder structures disposed above the wafer. A ball limiting metallurgy (BLM) layer disposed beneath each of the solder structures, above the wafer. At least one of the plurality of solder structures has a first composition, and at least another of the plurality of solder structures has a second composition.Type: ApplicationFiled: July 19, 2012Publication date: January 23, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles L. Arvin, Wolfgang Sauter, Jennifer D. Schuler