Abstract: Various embodiments provide systems, computer program products and computer implemented methods. Some embodiments include a system for modeling a relationship between a test time and a defect rate for a systematic multivariate issue caused by at least one predictable component and a random component in a semiconductor testing environment, the multivariate issue causing failure of a semiconductor device, the system that includes at least one computing device configured to perform actions including quantifying the at least one predictable component to produce at least one first mathematical form, quantifying the random component using distribution functions to produce a second mathematical form and producing a mathematical model of a relationship between the test time and the defect rate at a test condition by mathematically combining the at least one first mathematical form and the second mathematical form.

Abstract: A semiconductor structure is disclosed in which, in an embodiment, a first substrate includes at least one buried plate disposed in an upper part of the first substrate. Each of the at least one buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.

Abstract: A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.

Abstract: A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.

Abstract: A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.

Abstract: A method is disclosed of temperature compensation for measurement of a temperature sensitive parameter of semiconductor IC chips, particularly temperature compensation for a maximum frequency measurement (Fmax) and speed sort/categorization of semiconductor IC chips. The method includes determining a change of a temperature sensitive parameter of the chip with temperature; measuring the temperature sensitive parameter of the chip during testing of the chip; measuring the chip temperature directly during or following the measurement of the temperature sensitive parameter; and determining an adjusted temperature sensitive parameter of the chip based upon the measured temperature sensitive parameter of the chip during testing, the measured chip temperature, and the determined change of the temperature sensitive parameter of the chip with temperature.

Abstract: A method and circuit for tunneling leakage current compensation, the method including: forcing a current of known value through a tunneling current leakage monitor device to provide a voltage signal; and regulating an on-chip power supply of the integrated circuit chip based on the voltage signal.