Abstract: A crowd determined message response system may be provided. A message sent from a sender to at least one recipient over a communication network may be received. The message may be presented on a user interface device. A selection of a designated recipient for responding to the message may be received. A priority of the message sent to the designated recipient may be adjusted. The priority of the message sent to an unselected recipient of the message not selected as the designated recipient may be adjusted. The priority may be adjusted differently for the designated recipient and the unselected recipient. Based on the adjusting of the priority of the message sent to the unselected recipient, the order of importance in which the unselected recipient's messages are presented may be rearranged.

Abstract: A crowd determined message response system may be provided. A message sent from a sender to at least one recipient over a communication network may be received. The message may be presented on a user interface device. A selection of a designated recipient for responding to the message may be received. A priority of the message sent to the designated recipient may be adjusted. The priority of the message sent to an unselected recipient of the message not selected as the designated recipient may be adjusted. The priority may be adjusted differently for the designated recipient and the unselected recipient. Based on the adjusting of the priority of the message sent to the unselected recipient, the order of importance in which the unselected recipient's messages are presented may be rearranged.

Abstract: A crowd determined message response system may be provided. A message sent from a sender to at least one recipient over a communication network may be received. The message may be presented on a user interface device. A selection of a designated recipient for responding to the message may be received. A priority of the message sent to the designated recipient may be adjusted. The priority of the message sent to an unselected recipient of the message not selected as the designated recipient may be adjusted. The priority may be adjusted differently for the designated recipient and the unselected recipient. Based on the adjusting of the priority of the message sent to the unselected recipient, the order of importance in which the unselected recipient's messages are presented may be rearranged.

Abstract: A crowd determined message response system may be provided. A message sent from a sender to at least one recipient over a communication network may be received. The message may be presented on a user interface device. A selection of a designated recipient for responding to the message may be received. A priority of the message sent to the designated recipient may be adjusted. The priority of the message sent to an unselected recipient of the message not selected as the designated recipient may be adjusted. The priority may be adjusted differently for the designated recipient and the unselected recipient. Based on the adjusting of the priority of the message sent to the unselected recipient, the order of importance in which the unselected recipient's messages are presented may be rearranged.

Abstract: A computer system is provided with a processing chip having one or more processor cores, with the processing chip in communication with an operating system having kernel space and user space. Each processor core has multiple core threads to share resources of the core, with each thread managed by the operating system to function as an independent logical processor within the core. A logical extended map of the processor core is created and supported, with the map including each of the core threads indicating usage of the operating system, including user space and kernel space, and cache, memory, and non-memory. An operating system scheduling manager is provided to schedule a routine on the processor core by allocating the routine to different core threads based upon thread availability as demonstrated in the map, and thread priority.

Abstract: A method and apparatus to improve memory initialization in a memory of a computer system. Memory units in the memory comprise a plurality of ranks, each rank having a unique rank select. A parity generator outputs a parity bit corresponding to whether an encoded rank select has an even or odd number of “1”s. The parity bit is used by an Error Checking and Correcting (ECC) unit that generates ECC bits that are stored in a rank having an active rank select. During a first interval in a memory initialization period, ranks having an even number of “1”s in their encoded rank select are initialized in parallel. During a second interval in the memory initialization period, ranks having an odd number of “1”s in their encoded rank select are initialized in parallel.

Abstract: A computer system is provided with a processing chip having one or more processor cores, with the processing chip in communication with an operating system having kernel space and user space. Each processor core has multiple core threads to share resources of the core, with each thread managed by the operating system to function as an independent logical processor within the core. A logical extended map of the processor core is created and supported, with the map including each of the core threads indicating usage of the operating system, including user space and kernel space, and cache, memory, and non-memory. An operating system scheduling manager is provided to schedule a routine on the processor core by allocating the routine to different core threads based upon thread availability as demonstrated in the map, and thread priority.

Abstract: A method and apparatus to improve memory initialization in a memory of a computer system. Memory units in the memory comprise a plurality of ranks, each rank having a unique rank select. A parity generator outputs a parity bit corresponding to whether an encoded rank select has an even or odd number of “1”s. The parity bit is used by an Error Checking and Correcting (ECC) unit that generates ECC bits that are stored in a rank having an active rank select. During a first interval in a memory initialization period, ranks having an even number of “1”s in their encoded rank select are initialized in parallel. During a second interval in the memory initialization period, ranks having an odd number of “1”s in their encoded rank select are initialized in parallel.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to out-of-band management of system fault handling and provide a novel and non-obvious method, system and computer program product for recovering diagnostic data after out-of-band data capture failure. In an embodiment of the invention, a method for recovering diagnostic data after out-of-band data capture failure can include detecting an uncorrectable error in a coupled CPU. Thereafter, the coupled CPU can be placed in a quiesced state and the CPU can be warm reset. Error data can be retrieved from the CPU registers for the CPU and the CPU can be rebooted. Finally, the quiesced state of the CPU can be removed.