Abstract: An insulated fenestration system includes a frame comprising a first bracket, the first bracket defining a sealing slot; a pane assembly assembled with the frame, the pane assembly comprising a first pane; a bracket gap defined between the first bracket and the first pane; and a first seal engaging the sealing slot, the first seal extending across the bracket gap and abutting the first pane.

Abstract: In some embodiments, an electronic device presents media items from different media applications in a unified media browsing application. In some embodiments, an electronic device facilitates browsing of media from different media applications based on category of media (e.g., movies, television shows, etc.). In some embodiments, an electronic device facilitates setup of a unified media browsing application that presents media items from different media applications in a unified media browsing user interface. In some embodiments, an electronic device displays multiple episodes of a collection of episodic content (e.g., a television series) in a user interface for the collection of episodic content. In some embodiments, an electronic device displays representations of, and provides access to, live-event media items accessible on the electronic device.

Abstract: A method of assembling a portal can include obtaining a stile, wherein the stile can include a first stile and a second stile; arranging a thermal strut and insulative bar between the first stile and the second stile, wherein the insulative bar can define a lock groove; arranging a lock assembly within the lock groove, wherein the lock assembly can include a fastening plate rotatably coupled to the lock assembly; and coupling the lock assembly to the stile by rotating the fastening plate and, thereafter, engaging fasteners to provide friction between the fastening plate and the insulative bar.

Abstract: Example aspects of a simulated steel fenestration system, an insulated fenestration system, and a method for insulating a fenestration system are disclosed. The simulated steel fenestration system can comprise a frame, a pane assembly assembled with the frame, and a muntin bar, wherein at least one of the frame and the muntin bar comprise a non-steel material configured to resemble steel.

Abstract: Example aspects of a simulated steel fenestration system, an insulated fenestration system, and a method for insulating a fenestration system are disclosed. The simulated steel fenestration system can comprise a frame, a pane assembly assembled with the frame, and a muntin bar, wherein at least one of the frame and the muntin bar comprise a non-steel material configured to resemble steel.

Abstract: Example aspects of a shear plate for a window frame assembly, a window frame assembly, and a method for insulating a window frame assembly are disclosed. The shear plate for a window frame assembly can comprise a shear plate body defining an outer shear plate surface and an inner shear plate surface, the shear plate body defining a first end, a second end opposite the first end, and a pair of lateral sides extending between the first end and the second end; and at least one pair of shear plate holes extending from the outer shear plate surface to the inner shear plate surface, the pair of shear plate holes oriented such that a line running through a center of the pair of shear plate holes is substantially parallel to the first end and the second end.

Abstract: A portal can include at least one rail and at least one stile, each end of each rail connected to an end of each stile such that the portal defines a frame, wherein at least one stile can include a first stile and a second stile; a thermal strut arranged between the first stile and the second stile, the thermal strut being of an insulating material; and an insulative bar arranged between the first stile and the second stile, the insulative bar being of an insulating material.

Abstract: Methods of producing high purity palmitoleic acid esters from natural oils are disclosed. The natural oils may comprise plant oil, nut oil, microalgae oil, and fish oil. The methods of processing the natural oil comprise transesterification with ethanol as the reacting solvent to produce ethyl esters. Methods of producing a high purity fraction of Omega-3, 6, & 9 fatty acid esters from natural oils are also disclosed. The high purity fatty acid esters may be used in nutrition, cosmetic, and nutraceutical products.

Abstract: Methods of producing high purity palmitoleic acid esters from natural oils are disclosed. The natural oils may comprise plant oil, nut oil, microalgae oil, and fish oil. The methods of processing the natural oil comprise transesterification with ethanol as the reacting solvent to produce ethyl esters. Methods of producing a high purity fraction of Omega-3, 6, & 9 fatty acid esters from natural oils are also disclosed. The high purity fatty acid esters may be used in nutrition, cosmetic, and nutraceutical products.

Abstract: Methods of producing high purity palmitoleic acid esters from natural oils are disclosed. The natural oils may comprise plant oil, nut oil, microalgae oil, and fish oil. The methods of processing the natural oil comprise transesterification with ethanol as the reacting solvent to produce ethyl esters. Methods of producing a high purity fraction of Omega-3, 6, & 9 fatty acid esters from natural oils are also disclosed. The high purity fatty acid esters may be used in nutrition, cosmetic, and nutraceutical products.

Abstract: Methods of producing high purity palmitoleic acid esters from natural oils are disclosed. The natural oils may comprise plant oil, nut oil, microalgae oil, and fish oil. The methods of processing the natural oil comprise transesterification with ethanol as the reacting solvent to produce ethyl esters. Methods of producing a high purity fraction of Omega-3, 6, & 9 fatty acid esters from natural oils are also disclosed. The high purity fatty acid esters may be used in nutrition, cosmetic, and nutraceutical products.

Abstract: Apparatus and methods for equalization are provided. In one embodiment, an apparatus for equalizing an input voltage includes a first capacitor and a first resistor having a first end and a second end, the first end configured to receive the input voltage. The apparatus further includes a second resistor having a first end electrically connected to the second end of the first resistor at an output node. The apparatus further includes an inverting voltage buffer for substantially inverting the input voltage to generate an inverted input voltage. The apparatus further includes a transconductance buffer for receiving the inverted input voltage and for generating a current from a first end of the first capacitor to the output node having a magnitude equal to about the magnitude of the input voltage signal divided by the impedance of the first capacitor.

Abstract: As provided herein, in some embodiments, power consumption and/or chip area is reduced by bias circuits configured to provide bias conditions for more than one active circuit, thereby reducing the number of bias circuits in a design. Shared bias circuits may reduce the aggregate amount of on-chip area utilized by bias circuitry and may also reduce the total power consumption of a chip. Additionally and/or alternatively, bias circuits disclosed herein are configured to provide outputs that are less susceptible to changes in the voltage supply level. In particular, in some embodiments, bias circuits are configured to provide relatively constant bias conditions despite changes in the voltage supply level. In some embodiments, bias circuits are configured to provide bias conditions that compensate for perturbations caused by changes other inputs, in order to stabilize a particular operating point.

Abstract: As provided herein, in some embodiments, power consumption and/or chip area is reduced by bias circuits configured to provide bias conditions for more than one active circuit, thereby reducing the number of bias circuits in a design. Shared bias circuits may reduce the aggregate amount of on-chip area utilized by bias circuitry and may also reduce the total power consumption of a chip. Additionally and/or alternatively, bias circuits disclosed herein are configured to provide outputs that are less susceptible to changes in the voltage supply level. In particular, in some embodiments, bias circuits are configured to provide relatively constant bias conditions despite changes in the voltage supply level. In some embodiments, bias circuits are configured to provide bias conditions that compensate for perturbations caused by changes other inputs, in order to stabilize a particular operating point.

Abstract: Apparatus and methods for equalization are provided. In one embodiment, an apparatus for equalizing an input voltage includes a first capacitor and a first resistor having a first end and a second end, the first end configured to receive the input voltage. The apparatus further includes a second resistor having a first end electrically connected to the second end of the first resistor at an output node. The apparatus further includes an inverting voltage buffer for substantially inverting the input voltage to generate an inverted input voltage. The apparatus further includes a transconductance buffer for receiving the inverted input voltage and for generating a current from a first end of the first capacitor to the output node having a magnitude equal to about the magnitude of the input voltage signal divided by the impedance of the first capacitor.

Abstract: As provided herein, in some embodiments, power consumption and/or chip area is reduced by bias circuits configured to provide bias conditions for more than one active circuit, thereby reducing the number of bias circuits in a design. Shared bias circuits may reduce the aggregate amount of on-chip area utilized by bias circuitry and may also reduce the total power consumption of a chip. Additionally and/or alternatively, bias circuits disclosed herein are configured to provide outputs that are less susceptible to changes in the voltage supply level. In particular, in some embodiments, bias circuits are configured to provide relatively constant bias conditions despite changes in the voltage supply level. A bias circuit arrangement with an output substantially decoupled from changes in the voltage supply level may provide a more stable operating point in an active circuit.

Abstract: As provided herein, in some embodiments, power consumption and/or chip area is reduced by bias circuits configured to provide bias conditions for more than one active circuit, thereby reducing the number of bias circuits in a design. Shared bias circuits may reduce the aggregate amount of on-chip area utilized by bias circuitry and may also reduce the total power consumption of a chip. Additionally and/or alternatively, bias circuits disclosed herein are configured to provide outputs that are less susceptible to changes in the voltage supply level. In particular, in some embodiments, bias circuits are configured to provide relatively constant bias conditions despite changes in the voltage supply level. A bias circuit arrangement with an output substantially decoupled from changes in the voltage supply level may provide a more stable operating point in an active circuit.

Abstract: In embodiments of the present invention, the problems of poor low-frequency response, slow speed, high cost and high power consumption in conventional voltage translators are addressed by processing high frequency and low frequency components of an input signal separately in two parallel stages without the use of large passive components or slow devices. At the output, the processed high frequency and low frequency components are seamlessly merged at a combining stage that maintains the integrity of the frequency response over the complete translator bandwidth.

Abstract: In embodiments of the present invention, the problems of poor low-frequency response, slow speed, high cost and high power consumption in conventional voltage translators are addressed by processing high frequency and low frequency components of an input signal separately in two parallel stages without the use of large passive components or slow devices. At the output, the processed high frequency and low frequency components are seamlessly merged at a combining stage that maintains the integrity of the frequency response over the complete translator bandwidth.

Abstract: A system and method of calibration develops a function from which is generated a monotonic time response; a gating period is defined from the monotonic time response and any error in the frequency of a reference signal is determined during the gating period; from that error an error signal is generated for adjusting the time constant of a circuit to be calibrated.