Abstract: Efficient and effective testing systems and methods are presented. In one embodiment, a testing system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester manages testing of the plurality of DUTs, including managing CXL protocol aspects of the testing. In one exemplary implementation, the tester prevents testing of a first one of the plurality of DUTs from detrimentally interfering with testing of a second one of the plurality of DUTs.

Abstract: Efficient and effective testing systems and methods are presented. In one embodiment, a system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester is configured to enable hot add of one of the plurality of DUTs without interfering with testing of the other DUTS. In one exemplary implementation, the DUTs are memory devices and the DUTs can operate as extended memory. The user interface can be utilized to indicate a pause to remove a DUT and to indicate a DUT has been added and to trigger a re-start. The added one of the plurality of DUTs can be automatically recognized by a host in a way that is transparent to users. The tester automatically directs the hot add in response to a user trigger.

Abstract: The present disclosure generally relates to methods and user interfaces for managing visual content at a computer system. In some embodiments, methods and user interfaces for managing visual content in media are described. In some embodiments, methods and user interfaces for managing visual indicators for visual content in media are described. In some embodiments, methods and user interfaces for inserting visual content in media are described. In some embodiments, methods and user interfaces for identifying visual content in media are described. In some embodiments, methods and user interfaces for translating visual content in media are described.

Abstract: A calibrating method for adjusting related parameters when a first chip and a second chip switch signals is disclosed. The calibrating method includes: utilizing the first chip to output a test signal through using a first driving force in order to represent a test value; utilizing the second chip to receive the test signal and utilizing the second chip to read the test signal to determine a value; and performing a comparison step for comparing the value with the test value to detect whether said value complies with the test value.

Abstract: A clock signal detector is provided. The device comprises a plurality of signal delayers and a plurality of flip-flops for comparing the offset range of the clock signal between two different groups, and transmitting the resulted signal to a phase compensator, which is used to send a regulating clock signal to a clock generator. Therefore, the offset ranges of the clock signals from two different groups will be within the range of the system requirement, such that it can optimize the system operation.

Abstract: A controlling method of logic operations is used to control a plurality of logics inside a chip, which is in a power peak state. The controlling method comprises the following steps of: providing a control signal to the chip, controlling at least one of the logics based on the control signal at a first timing, and controlling at least another one of the logics based on the control signal at a second timing. The control signal is intent to substantially control actions of the logics synchronously. Moreover, a mainboard and an electronic component, utilizing the controlling method of logic operations, are provided.

Abstract: A voltage monitoring circuit is capable of being integrated into a chip and monitoring the voltage quality. It mainly uses a first waveshaper to receive a voltage signal of a voltage source to be measured, process it to a logic signal, and output to a first logic level transformer. A first digital signal is transformed by the processing and can be recorded by a register such that a managing system can read content of the register through a bus to further determine whether the voltage source has a situation of voltage surge. Similarly, an inverter can be concatenated between a second waveshaper and a second logic level transformer to monitor whether the voltage source has undercurrent pulse. This way, an object of monitoring voltage quality in the chip with a combination of simple analog circuit can be achieved.

Abstract: A clock signal detector is provided. The device comprises a plurality of signal delayers and a plurality of flip-flops for comparing the offset range of the clock signal between two different groups, and transmitting the resulted signal to a phase compensator, which is used to send a regulating clock signal to a clock generator. Therefore, the offset ranges of the clock signals from two different groups will be within the range of the system requirement, such that it can optimize the system operation.

Abstract: A method and system for transferring raster/image data via a mail user agent using a multifunction device and standard Internet mail transfer mechanisms. An image is acquired in the multifunction device, the image is attached to an electronic mail message, and then sent in the electronic mail message to receiving address(es). Alternatively, an electronic mail box is polled by a mail user agent, which identifies those received messages with raster/image attachment(s) and downloads the attachment(s) to the multifunction device for printing, displaying and/or workflow insertion.

Abstract: A calibrating method for adjusting related parameters when a first chip and a second chip switch signals is disclosed. The calibrating method includes: utilizing the first chip to output a test signal through using a first driving force in order to represent a test value; utilizing the second chip to receive the test signal and utilizing the second chip to read the test signal to determine a value; and performing a comparison step for comparing the value with the test value to detect whether said value complies with the test value.

Abstract: A voltage monitoring circuit is capable of being integrated into a chip and monitoring the voltage quality. It mainly uses a first waveshaper to receive a voltage signal of a voltage source to be measured, process it to a logic signal, and output to a first logic level transformer. A first digital signal is transformed by the processing and can be recorded by a register such that a managing system can read content of the register through a bus to further determine whether the voltage source has a situation of voltage surge. Similarly, an inverter can be concatenated between a second waveshaper and a second logic level transformer to monitor whether the voltage source has undercurrent pulse. This way, an object of monitoring voltage quality in the chip with a combination of simple analog circuit can be achieved.

Abstract: A controlling method of logic operations is used to control a plurality of logics inside a chip, which is in a power peak state. The controlling method comprises the following steps of: providing a control signal to the chip, controlling at least one of the logics based on the control signal at a first timing, and controlling at least another one of the logics based on the control signal at a second timing. The control signal is intent to substantially control actions of the logics synchronously. Moreover, a mainboard and an electronic component, utilizing the controlling method of logic operations, are provided.

Abstract: A carrying case includes a carrying member disposed on a top portion of a housing. The carrying member includes a first carrying body having a driving end opposite to a first pivot end connected pivotally to one lateral side of the housing, and a second carrying body having a driven end opposite to a second pivot end connected pivotally to the other lateral side of the housing. The first carrying body has a first width measured between the first pivot end and the driving end and greater than a second width of the second carrying body measured between the second pivot end and the driven end, and is provided with a handgrip thereon. An anchoring unit retains releasably the first and second carrying bodies at a closed position.

Abstract: A method and system for transferring raster/image data via a mail user agent using a multifunction device and standard Internet mail transfer mechanisms. An image is acquired in the multifunction device, the image is attached to an electronic mail message, and then sent in the electronic mail message to receiving address(es). Alternatively, an electronic mail box is polled by a mail user agent, which identifies those received messages with raster/image attachment(s) and downloads the attachment(s) to the multifunction device for printing, displaying and/or workflow insertion.

Abstract: Disclosed is a semiconductor package characterized by having at least one cavity defined in a substrate and at least one buffer pad disposed in the at least one cavity. The semiconductor package includes a semiconductor chip disposed on the substrate, at least one conductive trace connecting with the buffer pad and at least one bonding wire electrically connecting the semiconductor chip to the buffer pad. The buffer pad has a thickness larger than the thickness of the conductive trace.

Abstract: Disclosed is a semiconductor package characterized by having at least one cavity defined in a substrate and at least one buffer pad disposed in the at least one cavity. The semiconductor package includes a semiconductor chip disposed on the substrate, at least one conductive trace connecting with the buffer pad and at least one bonding wire electrically connecting the semiconductor chip to the buffer pad. The buffer pad has a thickness larger than the thickness of the conductive trace.

Abstract: The present invention concerns the use of methods and compositions for diagnosis, prognosis, and treatment of HIV infection and AIDS using thymidine phosphorylase as an indicator.