Abstract: An imaging system with image data path delay measurement includes (a) a first image sensor chip that includes a pixel array for generating a first image in response to light incident upon the pixel array, and a time mark generator for, upon receiving a time mark command, encoding a signature in the first image to generate a first marked image with the signature and image data from the first image, and (b) an image signal processing chip for processing the first marked image, wherein the image signal processing chip includes a data path delay measurement module for generating the time mark command and estimating image data path delay from the pixel array to the data path delay measurement module based upon time delay between (i) generating the time mark command and (ii) receipt of the signature as part of the first marked image.

Abstract: An imaging system with image data path delay measurement includes (a) a first image sensor chip that includes a pixel array for generating a first image in response to light incident upon the pixel array, and a time mark generator for, upon receiving a time mark command, encoding a signature in the first image to generate a first marked image with the signature and image data from the first image, and (b) an image signal processing chip for processing the first marked image, wherein the image signal processing chip includes a data path delay measurement module for generating the time mark command and estimating image data path delay from the pixel array to the data path delay measurement module based upon time delay between (i) generating the time mark command and (ii) receipt of the signature as part of the first marked image.

Abstract: A system has in an integrated circuit a seed memory coupled to seed a vector generator that provides a vector to at least one scan chain of a first functional unit. A signature generator is configured to generate a signature from scan chain data, the signature is compared to an expected signature in a signature memory. A state memorizer is provided for saving a state of the functional unit and to restore the state of the functional unit as testing is completed. The system also has apparatus configured to determine an idle condition of the functional unit despite a non-idle state of the system; and a control unit configured to operate a test sequence when the functional unit is idle, the test sequence saving a state of the unit, generating vectors and signatures and verifying the signatures, and restoring the state of the unit.

Abstract: A method for testing an electronic memory while the memory is in use includes: (a) detecting an access to the electronic memory at a test address, (b) saving, in a register subsystem, write data written to the electronic memory at a location corresponding to the test address, (c) comparing the write data to data read from the electronic memory at the location corresponding to the test address to determine whether the memory has a fault, and (d) generating an error signal if the memory has a fault.

Abstract: A system has in an integrated circuit a seed memory coupled to seed a vector generator that provides a vector to at least one scan chain of a first functional unit. A signature generator is configured to generate a signature from scan chain data, the signature is compared to an expected signature in a signature memory. A state memorizer is provided for saving a state of the functional unit and to restore the state of the functional unit as testing is completed. The system also has apparatus configured to determine an idle condition of the functional unit despite a non-idle state of the system; and a control unit configured to operate a test sequence when the functional unit is idle, the test sequence saving a state of the unit, generating vectors and signatures and verifying the signatures, and restoring the state of the unit.

Abstract: A method for testing an electronic memory while the memory is in use includes: (a) detecting an access to the electronic memory at a test address, (b) saving, in a register subsystem, write data written to the electronic memory at a location corresponding to the test address, (c) comparing the write data to data read from the electronic memory at the location corresponding to the test address to determine whether the memory has a fault, and (d) generating an error signal if the memory has a fault.