Patents by Inventor Jenping Lin

Jenping Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of making LDD with polysilicon and dielectric spacers
    Patent number: 5498555
    Abstract: An improved FET device in which the hot carrier immunity and current driving capability are improved, and the subthreshold leakage current is minimized. The device has a gate electrode with vertical sidewalls, and a thin layer of SiO.sub.2 over the electrode. A first polysilicon spacer is provided on the vertical sidewalls, with a second overlying oxide spacer over the first spacer. The top portion of the SiO.sub.2 layer between the gate electrode and the polysilicon spacer is made conductive enough to keep the gate electrode and the polysilicon spacer at the same potential. Lightly doped source and drain regions are provided.
    Type: Grant
    Filed: November 7, 1994
    Date of Patent: March 12, 1996
    Assignee: United Microelectronics Corporation
    Inventor: Jenping Lin