Abstract: A probabilistic framework for compiler optimization with multithread power-gating controls includes scheduling all thread fragments of a multithread computer code with the estimated execution time, logging all time stamps of events, and sorting and unifying the logged time stamps. Time slices are constructed using adjacent time stamps of each thread fragment. A power-gating time having a component turned off for each time slice is determined. Power-gateable windows that reduce energy consumption of the time slice is determined according to the power-gating time. The compiler inserts predicated power-gating instructions at locations corresponding to the selected power-gateable windows into the power-gateable computer code.

Abstract: A method of allocating registers, includes for each of a plurality of live ranges of variables, calculating an energy saving value of each of the plurality of live ranges of the variables; classifying the plurality of live ranges of the variables into a plurality of queues according to the energy saving values of the plurality of live ranges of the variables; and assigning the plurality of live ranges of the variables in the plurality of queues into a plurality of registers.

Abstract: A method of allocating registers, includes for each of a plurality of live ranges of variables, calculating an energy saving value of each of the plurality of live ranges of the variables; classifying the plurality of live ranges of the variables into a plurality of queues according to the energy saving values of the plurality of live ranges of the variables; and assigning the plurality of live ranges of the variables in the plurality of queues into a plurality of registers.

Abstract: The present invention provides an affine engine design to the microarchitecture of the graphic processing unit, in which an operand type detection is performed, and then physical scalar, affine, or vector registers and corresponding ALUs with maximum performance improving and energy saving are allocated to perform instruction execution. In runtime, affine and uniform instructions are executed by the affine engine, while general vector instructions are executed by a vector engine, thereby the affine/uniform instruction execution can be dispatched to the affine engine, so the vector engine can enter a power-saving state to save the energy consumption of the GPU.

Abstract: A probabilistic framework for compiler optimization with multithread power-gating controls includes scheduling all thread fragments of a multithread computer code with the estimated execution time, logging all time stamps of events, and sorting and unifying the logged time stamps. Time slices are constructed using adjacent time stamps of each thread fragment. A power-gating time having a component turned off for each time slice is determined. Power-gateable windows that reduce energy consumption of the time slice is determined according to the power-gating time. The compiler inserts predicated power-gating instructions at locations corresponding to the selected power-gateable windows into the power-gateable computer code.

Abstract: A projecting device includes a wireless controller configured for wirelessly detecting a gesture and accordingly generating a wireless signal; and a projector configured for receiving the wireless signal and accordingly controlling a projection image projected by the projector.

Abstract: A method comprises generating an intermediate representation of a pointer-based program; providing a control flow graph of the intermediate representation; selecting an analysis candidate from the intermediate representation as a traced variable and a root node; determining a definition site of the trace variable according to a use-define chain and the control flow graph; defining a node for each definition site variable; defining an edge by using each definition site variable and the traced variable; using each definition site variable of the definition site as a traced variable; repeating the steps of determining a definition site, defining a node, defining an edge and using each definition site to obtain a divergence relation graph; transforming the divergence relation graph into a directed acyclic graph; and determining whether the analysis candidate is divergent or not according to a divergent node and the directed acyclic graph.

Abstract: A method for code size reduction, which comprises determining basic blocks in an IR module; grouping the basic blocks having duplicate code into groups; providing weighting values corresponding to different instructions of the module, wherein the weighting values are determined based on a plurality of intermediate representation program codes; determining a weighted size of the module, wherein the weighted size of the module is determined by summing weighted sizes of the basic blocks of the module, and the weighted size of each basic block is determined by summing products of numbers of different instructions of the basic blocks and the corresponding weighting values; removing duplicates in one group to obtain a module having one processed group; determining a weighted size of the module having one processed group; and comparing the weighted size of the module to the weighted size of the module having one processed group.

Abstract: A transpose unit of an apparatus comprises a plurality of banks each having a plurality of storage units, a write circuit, a plurality of selectors, and a parallel-to-serial circuit. The write circuit is configured to perform selections on the plurality of banks for storing data from a source memory. Each selector comprises an output and a plurality of inputs respectively coupled with the plurality of storage units of a corresponding bank, and the outputs of the plurality of selectors connect in parallel with the parallel-to-serial circuit. The parallel-to-serial circuit has a serial output connecting to a destination memory.

Abstract: A method comprises generating an intermediate representation of a pointer-based program; providing a control flow graph of the intermediate representation; selecting an analysis candidate from the intermediate representation as a traced variable and a root node; determining a definition site of the trace variable according to a use-define chain and the control flow graph; defining a node for each definition site variable; defining an edge by using each definition site variable and the traced variable; using each definition site variable of the definition site as a traced variable; repeating the steps of determining a definition site, defining a node, defining an edge and using each definition site to obtain a divergence relation graph; transforming the divergence relation graph into a directed acyclic graph; and determining whether the analysis candidate is divergent or not according to a divergent node and the directed acyclic graph.

Abstract: A computer system is provided. The computer system includes multiple computing devices and a processing unit. The processing unit comprises a device monitoring module, a task classifying module and a task scheduling module. The processing unit is coupled to the computing devices. The device monitoring module is configured to monitor the computing devices so as to obtain loading data. The task classifying module is configured to classify related tasks of multiple tasks as a first group, to classify independent tasks of multiple tasks as a second group and to find a critical path of the related tasks in the first group. The task scheduling module is configured to set a first processing schedule of the first group according to the critical path and the loading data and to set a second processing schedule of the second group according to the first processing schedule.

Abstract: A method for determining a logarithmic functional unit comprises providing a segment number; using the segment number to determine a piecewise linear approximation on a plurality of corresponding intervals for approximating a function for converting a fraction; providing a bit precision; converting endpoints separating the plurality of intervals to corresponding binary endpoints separating an additional plurality of intervals in the bit precision; determining an adjusted piecewise linear approximation that has an approximation error less than a threshold and is on the additional plurality of intervals; encoding coefficients of the adjusted piecewise linear approximation; determining a less precise approximation from the adjusted piecewise linear approximation as a candidate linear approximation, wherein the less precise approximation uses an argument value having a least bit-width while still being able to have an approximation error less than the threshold; and implementing the less precise approximation to

Abstract: A method for code size reduction, which comprises determining basic blocks in an IR module; grouping the basic blocks having duplicate code into groups; providing weighting values corresponding to different instructions of the module, wherein the weighting values are determined based on a plurality of intermediate representation program codes; determining a weighted size of the module, wherein the weighted size of the module is determined by summing weighted sizes of the basic blocks of the module, and the weighted size of each basic block is determined by summing products of numbers of different instructions of the basic blocks and the corresponding weighting values; removing duplicates in one group to obtain a module having one processed group; determining a weighted size of the module having one processed group; and comparing the weighted size of the module to the weighted size of the module having one processed group.

Abstract: A computer-implemented probabilistic pointer analysis method using SSA form comprises the steps of: evaluating a program in an SSA form comprising a target pointer to determine pointer relations between the target pointer, a plurality of aliased pointers related to the target pointer and at least a probable location of the target pointer; and generating a direct probabilistic relation between the target pointer and the at least a probable location of the target pointer according to the pointer relation.

Abstract: A method for providing intrinsic supports for a VLIW DSP processor with distributed register files comprises the steps of: generating a program representation with cluster information on instructions of the DSP processor, wherein the cluster information is provided by a program with cluster intrinsic coding; identifying data stream operations indicating parallel instruction sequences applied on different data sets in the program representation; identifying data sharing relations indicating data shared by the data stream operations in the program representation; identifying data aggregation relations indicating results aggregated from the data stream operations in the program representation; and performing register allocation for the DSP processor according to the identified data stream operations, the data sharing relations and the data aggregation relations.

Abstract: A method of allocating registers for a processor based on cycle information is disclosed. The processor comprises a first cluster and a second cluster. Each cluster comprises a first functional unit, a second functional unit, a first local register file connected to the first functional unit, a second local register file connected to the second register file, and a global register file having a ping-pong structure formed by a first register bank and a second register bank. After building a Component/Register Type Associated Data Dependency Graph (CRTA-DDG), a functional unit assignment, register file assignment, ping-pong register bank assignment, and cluster assignment are performed to take full advantage of the properties of a processor as well as cycle information.

Abstract: A spilling method in register files for a processor is proposed. The processor with Parallel Architecture Core structure includes multiple clusters and a memory. Each cluster includes multiple function units (M-Unit and I-Unit), multiple local register files and a global register file. The local register files are used by the multiple function units, respectively. For a specified live range, the method includes calculating communication costs of the local register files and the global register file in each cluster, and communication cost of the memory for spilling the live range when spilling occurs; calculating use ratios of the local register files and the global register file in each cluster, and use ratio of the memory for the live range; and selecting one of the local register files and the global register file in each cluster and the memory for spilling the live range based on the communication costs and use ratios.

Abstract: A computer-implemented probabilistic pointer analysis method using SSA form comprises the steps of: evaluating a program in an SSA form comprising a target pointer to determine pointer relations between the target pointer, a plurality of aliased pointers related to the target pointer and at least a probable location of the target pointer; and generating a direct probabilistic relation between the target pointer and the at least a probable location of the target pointer according to the pointer relation.

Abstract: The current disclosure discloses a power aware simulation system comprising an embedded multi-core simulation module, a power abstract interpretation module and a C power estimation (CPE) power profiling module. The embedded multi-core simulation module comprises a plurality of digital signal processors (DSP), an external memory and a direct memory access. Each of the plurality of DSPs comprises a DSP core, an instruction cache and a local memory. The power abstract interpretation module is coupled to the plurality of DSPs, the external memory, the DMA and the CPE profiling module, respectively.

Abstract: A method of optimizing multi-set context switch for embedded processors includes the steps of partitioning a plurality of registers into a plurality of register sets based on a live-range-sensitive context-switch procedure that is associated with a usage frequency of each of the registers, storing contents of first target registers according to live set information of a current task, wherein the first target registers are selected from the register sets, determining a next task by an operating system and updating the live set information according to the next task, and restoring contents of second target registers according to the updated live set information, wherein the second target registers are selected from the register sets.