Abstract: A method for producing a power semiconductor component having a plurality of fins. The method includes: creating a plurality of mesas starting from a front side of a semiconductor substrate into a drift layer of the semiconductor substrate by means of etching, each mesa being arranged between a first trench and a second trench. Each mesa has a width greater than 500 nm. The method further includes applying a mask layer to the top side, the first side surface, the second side surface, the first trench bottom surface and the second trench bottom surface; creating a structured mask by removing the mask layer in certain regions, so that an exposed surface is created; creating fins by machining the exposed surface; removing the structured mask and completing the power semiconductor component.

Abstract: A vertical field effect transistor, including a drift region having a first conductivity type, a trench structure on or above the drift region, a shielding structure, and a source/drain electrode. The trench structure includes at least one side wall at which a field effect transistor (FET) channel region is formed. The FET channel region includes a III-V heterostructure for forming a two-dimensional electron gas at a boundary surface of the III-V heterostructure. The shielding structure is situated laterally adjacent to the at least one side wall of the trench structure and extends vertically into the drift region or vertically further in the direction of the drift region than the trench structure. The shielding structure has a second conductivity type that differs from the first conductivity type. The source/drain electrode is electroconductively connected to the III-V heterostructure of the trench structure and to the shielding structure.

Abstract: A semiconductor component with a semiconductor substrate. The semiconductor component has at least one source element, at least one drain element, and at least one field plate. In the semiconductor component, the at least one field plate encloses an edge of the semiconductor component and is electrically contacted with the drain element. A method for producing a semiconductor component is also described.

Abstract: A method for producing a power FinFET with two-part control electrodes. The method includes: creating a first structured mask including oxide regions and first and second open regions on the front side of a semiconductor body via lithography; creating first and second trenches below the first and second open regions, respectively, by a first etching process starting from the front side of the semiconductor body into the drift layer, the first and second trenches being arranged substantially parallel to one another and alternate, the second trenches have a smaller width than the first trenches; applying a polysilicon layer onto the front side so that the first and second trenches are filled; applying an isotropic oxide layer onto the front side of the semiconductor body; creating a second structured mask on the isotropic oxide layer via lithography, wherein the second structured mask is open above the first trenches.

Abstract: A method for producing a power FinFET with two-part control electrodes. The power FinFET includes a semiconductor body, which includes a first connection region, a drift layer, a channel region and a second connection region. The method includes producing trenches, which extend from the second connection region into the drift layer, the trenches being arranged substantially in parallel with one another; producing shielding regions below the trenches using an implantation process, so that a shielding region is arranged below each trench; widening the trenches using at least one etching process, so that fins are formed between the trenches, the fins having a width of less than 500 nm; and producing the two-part control electrodes, which are arranged within the trenches, so that one two-part control electrode is in each case arranged in each trench. Each two-part control electrode is electrically insulated from the shielding region below the trench.

Abstract: A power finFET. The power finFET has two-part control electrodes and a semiconductor body which has a drift layer, and a second connection region arranged above the drift layer. The first trenches and second trenches extend from the second connection region into the drift layer, and being arranged in an alternating manner, the second trenches having a smaller width than the first trenches. Shielding zones are arranged below the first trenches, the shielding zones directly adjoining the first trenches, and the shielding zones being connected to source regions in an electrically conductive manner. A two-part control electrode is arranged within the first trenches in each case, the two-part control electrode being electrically insulated from the shielding zone below the first trenches in each case. Fins are arranged between the first trenches and the second trenches, the fins having a width of at most 500 nm.

Abstract: A vertical field-effect transistor. The transistor includes: a drift region having a first conductivity type; a semiconductor fin on or over the drift region; and a source/drain electrode on or over the semiconductor fin, the semiconductor fin having an electrically conductive region that connects the source/drain electrode to the drift region in electrically conductive fashion, and having a limiting structure that is formed laterally next to the electrically conductive region and that extends from the source/drain electrode to the drift region, the limiting structure being set up to limit a conductive channel of the vertical field-effect transistor in the semiconductor fin to the area of the electrically conductive region.

Abstract: A method for producing vertical power transistors. The method includes: applying a dielectric layer to a semiconductor material; applying a first photoresist layer to the dielectric layer; creating first openings having a first width in the first photoresist layer exposing first regions of the dielectric layer; etching the first regions of the dielectric layer to at least a specified depth of the dielectric layer such that a first structured dielectric layer is created; removing the first photoresist layer; applying a second photoresist layer to the first structured dielectric layer; creating second openings having a second width in the second photoresist layer exposing second regions of the dielectric layer; etching the second regions of the dielectric layer up to a surface of the semiconductor material such that a second structured dielectric layer is created; removing the second photoresist layer; and creating the first trenches and the second trenches.

Abstract: Methods and structures for reducing process and final deformation of gallium nitride (GaN) semiconductor devices are provided. The methods include forming at least one multi-layered structure on at least one surface(s) a semiconductor substrate. The multi-layered structure(s) are formed by applying at least a first amorphous layer on at least one surface(s) of the semiconductor substrate, the first amorphous layer having a first thermal expansion coefficients (CTE), and applying a second amorphous layer on the first amorphous layer, the second amorphous layer having a second thermal expansion coefficient, different from the first thermal expansion coefficient.

Abstract: A gallium nitride (GaN) growth layer includes a first surface, a second surface, and a bulk region extending between the first and second surfaces, the bulk region having a polycrystalline material with coefficient of thermal expansion (CTE) of about 2-25 ppm/K above 800 K and one or more spinel compounds having formula (I):(ZnxCd1-x) (CryAl1-y)2O4 (I), where x and y are any number between 0 and 1, one of the first and second surfaces including a GaN epitaxial growth region.

Abstract: A method for producing a low-defect interface between a GaN semiconductor substrate and a gate dielectric of a GaN power transistor. The method includes: introducing at least one GaN semiconductor substrate into a device; generating a vacuum within the device; heating the device to a first temperature; performing a first temperature step at the first temperature, wherein a reactive medium is introduced into the device and has a first partial pressure; performing a second temperature step at a second temperature, wherein an inert medium is introduced into the device and has a second partial pressure, and generating the gate dielectric on the GaN semiconductor substrate.

Abstract: A method of manufacturing a structure for power electronics which includes epitaxially growing a GaN semiconductor layer is provided. The method includes growing buffer layers formed of AlN and AlxGa(1-x)N, wherein 0<x<1, on a Si substrate before growing the semiconductor layer on the buffer layers. The method also includes growing deformation compensation layers formed of SiO2, SiCxN(1-x), SiN, SiCxO(1-x), SiC, SiNxO(1-x), Al2O3, and/or Cr2O3, wherein 0<x<1, on the substrate opposite the semiconductor layer. The deformation compensation layers compensate for deformation of the structure that occurs while growing the semiconductor and buffer layers and deformation that occurs while cooling the structure. The method further includes estimating epitaxial growth stress, interface stress, and thermal stress of the structure, and adjusting the temperature and or thickness of the layers based on the estimated epitaxial growth stress, interface stress, and/or thermal stress.

Abstract: A field-effect transistor. The field-effect transistor includes: a source layer doped according to a first type, a drain layer doped according to the first type, a channel layer located vertically between the source layer doped according to the first type and the drain layer doped according to the first type, and a plurality of gate trenches, which extend in the vertical direction from the source layer doped according to the first type to the drain layer doped according to the first type, wherein a fin is formed between each two gate trenches, wherein side surfaces of the fin face the gate trenches, wherein the channel layer is formed in at least a portion of the fin, and wherein an additional layer doped according to a second type is applied at least to one of the side surfaces of the fin.

Abstract: A method for producing a field-effect transistor. The method includes: providing a starting material including: a plurality of gate trenches, wherein a fin is formed between respectively two gate trenches; modifying at least a part of a surface layer of the starting material, wherein the part of the surface layer includes side surface layers on side surfaces of the fins, which side surfaces face the gate trenches, in order to obtain a modified surface layer; and at least partially removing at least a part of the modified surface layer in such a way that a width of the fins is reduced.

Abstract: A method for producing vertical power semiconductor components. The method includes: applying a first side of a silicon wafer onto a subcarrier wafer, wherein a front side of the vertical power semiconductor components is arranged on the first side of the silicon wafer and the front side of the vertical power semiconductor components comprises a buffer layer and a drift layer; grinding the silicon wafer to a specific thickness; dry etching the silicon wafer; etching the buffer layer; implanting ions into the drift layer, wherein a contact semiconductor layer is formed; generating an ohmic contact by applying a metal layer onto the contact semiconductor layer; and removing the subcarrier wafer.

Abstract: A vertical transistor with an outer region and a membrane region. At least a portion of a semiconductor substrate is arranged in the outer region. The semiconductor substrate is structured in such a way that a rear trench is arranged in the membrane region. The rear trench is free of semiconductor substrate. A masking layer is arranged in the outer region and/or in the membrane region. A layer stack is arranged in the membrane region, wherein the layer stack includes at least one drift layer, at least one component-defining layer system, and at least one control terminal, preferably a gate electrode. The masking layer is configured such that the region on the masking layer is substantially free of the layer stack so that the lateral extension of the layer stack is adjusted by means of the masking layer.

Abstract: A transistor arrangement for power transistors with a fin structure. It is provided to lower the epitaxy layer of the transistor arrangements in an edge region surrounding the fin structure and to introduce shield implants and edge implants into the epitaxy layer after lowering.

Abstract: A field-effect transistor. The field-effect transistor includes: an n-doped source layer, an n-doped drain layer, a channel layer located vertically between the n-doped source layer and the n-doped drain layer, and several gate trenches extending vertically from the n-doped source layer to the n-doped drain layer and adjoining the channel layer. A fin is respectively formed between each two gate trenches, wherein at least two of the fins have different widths. A method for production is also described.

Abstract: A vertical semiconductor component, in particular transistor, with a drift layer and/or an active layer on the basis of gallium nitride (GaN), and at least two, preferably three, electrodes. At least one measuring electrode is formed at a lower vertical level than the at least one other electrode and is designed to be contactable from vertically above.

Abstract: A semiconductor component, in particular diode or transistor. The semiconductor component includes two electrodes configured vertically one above the other, a substrate (102) made of gallium nitride, and a shielding layer for forming a space charge zone for shielding of an electric field when the semiconductor component is connected in a blocking operation or reverse direction.