Abstract: A transistor arrangement for power transistors with a fin structure. It is provided to lower the epitaxy layer of the transistor arrangements in an edge region surrounding the fin structure and to introduce shield implants and edge implants into the epitaxy layer after lowering.

Abstract: A field-effect transistor. The field-effect transistor includes: an n-doped source layer, an n-doped drain layer, a channel layer located vertically between the n-doped source layer and the n-doped drain layer, and several gate trenches extending vertically from the n-doped source layer to the n-doped drain layer and adjoining the channel layer. A fin is respectively formed between each two gate trenches, wherein at least two of the fins have different widths. A method for production is also described.

Abstract: A vertical semiconductor component, in particular transistor, with a drift layer and/or an active layer on the basis of gallium nitride (GaN), and at least two, preferably three, electrodes. At least one measuring electrode is formed at a lower vertical level than the at least one other electrode and is designed to be contactable from vertically above.

Abstract: A semiconductor component, in particular diode or transistor. The semiconductor component includes two electrodes configured vertically one above the other, a substrate (102) made of gallium nitride, and a shielding layer for forming a space charge zone for shielding of an electric field when the semiconductor component is connected in a blocking operation or reverse direction.

Abstract: A semiconductor component designed as a vertical HEMT. The semiconductor component includes a substrate made of gallium nitride (GaN), a drift layer arranged thereon, and a heteroepitaxial structure which is arranged thereabove, is laterally contacted by source electrodes and is suitable for providing a conductive channel by forming a two-dimensional electron gas.

Abstract: A semiconductor component that is designed as a trench MISFET. The semiconductor component includes a substrate made of gallium nitride (GaN), a drift layer situated thereon, a barrier layer, and a source region situated thereabove. The source region includes a gate trench that extends from the source region into the underlying barrier layer.

Abstract: Vertical GaN power transistor unit cell. The vertical GaN power transistor unit cell including a drift layer and at least one field shielding region. The at least one field shielding region is regionally disposed in the drift layer and includes an intrinsically p-type material.

Abstract: A vertical field-effect transistor. The transistor includes: a drift region having a first conductivity type; a semiconductor fin on or over the drift region; and a source/drain electrode on or over the semiconductor fin, the semiconductor fin having an electrically conductive region that connects the source/drain electrode to the drift region in electrically conductive fashion, and having a limiting structure that is formed laterally next to the electrically conductive region and that extends from the source/drain electrode to the drift region, the limiting structure being set up to limit a conductive channel of the vertical field-effect transistor in the semiconductor fin to the area of the electrically conductive region.

Abstract: A bidirectional power transistor. The bidirectional power transistor has an AlGaN/GaN structure, a first gate structure and a second gate structure. A surface of the AlGaN/GaN structure has a depression having a first slanting sidewall and a second slanting sidewall. The depression has a width that is greater than a height of the depression. The first gate structure is situated on the first slanting sidewall and the second gate structure is situated on the second slanting sidewall.

Abstract: A vertical fin field-effect transistor. The transistor has a semiconductor fin, an n-doped source region, an n-doped drift region, an n-doped channel region in the semiconductor fin situated vertically between the source region and the drift region, a gate region horizontally adjacent to the channel region, a gate dielectric electrically insulating the gate region from the channel region, a boundary surface between the gate dielectric and the channel region having negative boundary surface charges, a p-doped gate shielding region situated below the gate region so that, given the vertical projection, the gate shielding region is situated within a surface limited by the gate dielectric, a source contact electrically conductively connected to the source region, and an electrically conductive region between the gate region and the p-doped gate shielding region. The p-doped gate shielding region is electrically conductively connected to the source contact by the electrically conductive region.

Abstract: A vertical field-effect transistor. The vertical field-effect transistor includes: a drift area; a first semiconductor fin on or above the drift area and electrically conductively connected thereto; a plurality of second semiconductor fins on or above the drift area, the plurality of second semiconductor fins being formed connected electrically nonconductively to the drift area, the plurality of second semiconductor fins being situated laterally adjacent to at least one side wall of the first semiconductor fin and being electrically conductively connected thereto; and a source/drain electrode, which is electrically conductively connected to the plurality of second semiconductor fins.

Abstract: A vertical field-effect transistor. The vertical field-effect transistor has: A first semiconductor layer, which has a p-type conductivity, on or over a drift region; a groove structure which penetrates the first semiconductor layer vertically, the groove structure having at least one side wall on which a field-effect transistor (FET)-channel region is formed, the FET-channel region having a III-V-heterostructure for forming a two-dimensional electron gas at an interface of the III-V-heterostructure; a source-drain electrode which is electroconductively connected to the III-V-heterostructure; and a contact structure at least partially on or over the drift region, which forms a Schottky- or hetero-contact at least with the drift region, the contact structure being electroconductively connected to the source-drain electrode, and at least the region lying vertically between the contact structure and the drift region being free of the first semiconductor layer.

Abstract: A MOSFET with saturation contact. The MOSFET with saturation contact includes an n-doped source region, a source contact, a contact structure, which extends from the source contact to the n-doped source region, and forms with the source contact a first conductive connection and forms with the n-doped source region a second conductive connection, a barrier layer and an insulating layer. The contact structure includes a section between the first conductive connection and the second conductive connection, which is embedded between the barrier layer and the dielectric layer and is configured in such a way that a two-dimensional electron gas is formed therein.

Abstract: A vertical field effect transistor. The vertical field effect transistor includes: a drift area including a first conductivity type; a semiconductor fin on or above the drift area, a source/drain electrode on or above the drift area; and a shielding structure, which is situated laterally adjacent to the at least one side wall of the semiconductor fin in the drift area, the shielding structure including a second conductivity type, which differs from the first conductivity type, and the semiconductor fin being electrically conductively connected to the source/drain electrode.

Abstract: A vertical field-effect transistor. The vertical field-effect transistor includes: a drift region, a semiconductor fin on or above the drift region, and a source/drain electrode on or above the semiconductor fin. The semiconductor fin includes at least one concave side wall in the region between the drift region and the source/drain electrode.

Abstract: A vertical field effect transistor. The vertical field effect transistor includes: a drift area; a semiconductor fin on or above the drift area; a connection area on or above the semiconductor fin; and a gate electrode, which is formed adjacent to at least one side wall of the semiconductor fin, the semiconductor fin, in a first section, which is situated laterally adjacent to the gate electrode, having a lesser lateral extension than in a second section, which contacts the drift area, and/or than in a third section, which contacts the connection area.

Abstract: A vertical field effect transistor. The vertical field effect transistor includes a trench structure having a first side and a second side opposite the first side. A field effect transistor (FET) channel is formed at the first side, and the second side is free of a FET channel. The FET channel includes a gallium nitride (GaN) region and an aluminum gallium nitride (AlGaN) region adjacent thereto. The GaN region includes a p-conductive first region and a second region formed thereon. The vertical field effect transistor also includes a source electrode that is electroconductively connected to the p-conductive first region of the GaN region and to the AlGaN region.

Abstract: A vertical field effect transistor, including a drift region having a first conductivity type, a trench structure on or above the drift region, a shielding structure, and a source/drain electrode. The trench structure includes at least one side wall at which a field effect transistor (FET) channel region is formed. The FET channel region includes a III-V heterostructure for forming a two-dimensional electron gas at a boundary surface of the III-V heterostructure. The shielding structure is situated laterally adjacent to the at least one side wall of the trench structure and extends vertically into the drift region or vertically further in the direction of the drift region than the trench structure. The shielding structure has a second conductivity type that differs from the first conductivity type. The source/drain electrode is electroconductively connected to the III-V heterostructure of the trench structure and to the shielding structure.