Abstract: A method for retransmission of erroneous data in a communications system includes receiving data blocks at a receiver that have been generated in a transmitter by the use of an error correcting code. The received data blocks are decoded by a linear programming algorithm. One or more symbols in the decoded data block are identified by subjecting the symbols in the decoded data block to an integrality criterion. A retransmission of a part of the data block based on the one or more identified symbols is then initiated.

Abstract: A method for detection of a control channel includes receiving data transmitted via the control channel. A control channel receive quality is estimated based on a metric difference between a metric of a known final trellis state and a minimum metric amongst the metrics of the trellis states based on the received data. It is decided whether or not to detect the control channel depending on the estimated control channel receive quality.

Abstract: Depending on the sequence of the decoded payload signal bits (am1, . . . , amA) and redundancy checking bits (pm1, . . . , pmL) which are produced by the Viterbi traceback, either some of these bits are inserted by means of a distribution device (1) from the front into a linear feedback shift register (10), or some of these bits are inserted by means of the distribution device (1) from the rear into a linear feedback shift register (10), or all of them are inserted into a linear feedback shift register (20) from the rear with the allocated coefficients being unchanged, or all of them are inserted into a shift register from the front with the allocated coefficients being inverted. This allows a redundancy checking process to be carried out on a transmitted data block in the shift register (10; 20) without temporary storage of the bits produced by the decoding process.

Abstract: A decoding apparatus includes at least one decoder both for a turbo-decoding and for a Viterbi decoding, at least one first data path for the Viterbi decoding of a convolution code, at least one second data path for the decoding of a turbo code, and a common memory having a multiplicity of individual memory areas. It is possible to allocate at least one memory area both through the first data path in the Viterbi mode and through the second data path in the turbo mode. The invention also includes a trellis processor and a method for operating a decoding apparatus in which at least parts of the first data path and of the second data path can be utilized jointly both for the turbo decoding and for the Viterbi decoding.

Abstract: In the method for termination of turbo decoding, a plurality of first LLR values (Lai(k)) of a-priori information and a plurality of second LLR values (Lei(k)) of extrinsic information are called up. A value is determined for a decision variable which is characteristic of the number of mathematical sign discrepancies between the first Lai(k)) and the second Lei(k)) values. The turbo decoding is terminated if the number of mathematical sign discrepancies is less than or at least equal to a first number or if the number is greater than or at least equal to a second number.

Abstract: Depending on the sequence of the decoded payload signal bits (am1, . . . , amA) and redundancy checking bits (pm1, . . . , pmL) which are produced by the Viterbi traceback, either some of these bits are inserted by means of a distribution device (1) from the front into a linear feedback shift register (10), or some of these bits are inserted by means of the distribution device (1) from the rear into a linear feedback shift register (10), or all of them are inserted into a linear feedback shift register (20) from the rear with the allocated coefficients being unchanged, or all of them are inserted into a shift register from the front with the allocated coefficients being inverted. This allows a redundancy checking process to be carried out on a transmitted data block in the shift register (10; 20) without temporary storage of the bits produced by the decoding process.

Abstract: A combined interleaving and deinterleaving circuit (IDL1) has a first data memory (RAM) for temporary storage of the data to be interleaved and deinterleaved. A first address generator produces a sequence of sequential addresses, and a second address generator (AG) produces a sequence of addresses which represents the interleaving rule (?(i)). A logic means (XOR, MUX) causes the data memory (RAM) to be addressed by the second address generator (AG) in the interleaving mode for a read process and in the deinterleaving mode for a write process.

Abstract: A method for calculation of path weights for the equalization of a data signal that is transmitted via a data channel whose power is regulated in a RAKE receiver is disclosed. In the method, at least one uncorrected path weight is calculated for the data signal that is transmitted via the data channel, using channel estimation results that have been obtained on the basis of a common pilot channel. The uncorrected path weight is corrected by multiplying it by a correction factor that contains a ratio of a data-channel-specific gain estimation to a pilot-channel-based gain estimation.

Abstract: A decoding apparatus includes at least one decoder both for a turbo-decoding and for a Viterbi decoding, at least one first data path for the Viterbi decoding of a convolution code, at least one second data path for the decoding of a turbo code, and a common memory having a multiplicity of individual memory areas. It is possible to allocate at least one memory area both through the first data path in the Viterbi mode and through the second data path in the turbo mode. The invention also includes a trellis processor and a method for operating a decoding apparatus in which at least parts of the first data path and of the second data path can be utilized jointly both for the turbo decoding and for the Viterbi decoding.