Abstract: An integrated circuit includes memory segments, each having at least one memory cell configurable in first and second states to store data, and a controller that controls programming and erasing of the memory segments. The controller maps external memory addresses of write data to internal memory addresses of erased memory segments with no memory cells in the first state such that erased memory segments are programmed with write data. When a write access occurs for an external memory address previously mapped to an internal memory address of a programmed memory segment with at least one memory cell in the first state, the controller remaps the external memory address to another internal memory address of an erased memory segment. The controller identifies programmed memory segments to be erased and controls selective erasure of the identified programmed memory segments, such as programmed memory segments no longer mapped to an external memory address.

Abstract: An integrated circuit includes memory segments, each having at least one memory cell configurable in first and second states to store data, and a controller that controls programming and erasing of the memory segments. The controller maps external memory addresses of write data to internal memory addresses of erased memory segments with no memory cells in the first state such that erased memory segments are programmed with write data. When a write access occurs for an external memory address previously mapped to an internal memory address of a programmed memory segment with at least one memory cell in the first state, the controller remaps the external memory address to another internal memory address of an erased memory segment. The controller identifies programmed memory segments to be erased and controls selective erasure of the identified programmed memory segments, such as programmed memory segments no longer mapped to an external memory address.

Abstract: The invention relates to a driver device and a method for operating a driver device in particular for a semiconductor device. The driver device includes a signal driver connected to a supply voltage. The driver device also includes a signal driver activating circuit section for activating a further signal driver when the supply voltage lies below a predetermined threshold value.

Abstract: A method and a device for regulating the threshold voltage of a transistor is disclosed. The device includes a circuit configured for modifying a voltage applied at a bulk connection of the transistor such that the threshold voltage of the transistor is substantially temperature-independent at least in a first temperature range. In one embodiment, the device includes a memory device, and the transistor is a transistor of a sense amplifier of the memory device.

Abstract: The invention is directed to a system and method comprising a first semiconductor device and a second semiconductor device, wherein the first semiconductor device comprises a voltage supply means, characterized in that the voltage supply means of the first semiconductor device is connected to the second semiconductor device, so that the voltage supply means of the first semiconductor device can provide a supply voltage for the second semiconductor device.

Abstract: An integrated semiconductor memory that has at least one temperature measuring element and repeatedly carries out a temperature measurement during the operation of the semiconductor memory, wherein the semiconductor memory repeats the temperature measurement at instants corresponding to a measuring frequency of the temperature measuring element. According to an embodiment of the invention, the measuring frequency of the temperature measuring element is variable and the temperature measuring element is driven in such a way that the measuring frequency changes in a manner dependent on the temporal development of measured values of the repeated temperature measurements.

Abstract: A method and a circuit are disclosed for determining the resistive state of a resistive memory cell being read. The method includes determining the resistive state of the memory cell being read by comparing a current dependent on the resistive state of the memory cell being read with a reference current that can be dependent on a resistive state of at least one reference resistive memory cell. A read circuit can be constructed to compare the two currents. The resistive state of the memory cell being read is indicative of the data bit stored by the memory cell.

Abstract: Methods and apparatus for determining a temperature of a memory device. A memory device includes a memory array, a temperature configured to measure a temperature of the device and an evaluating circuit configured to receive a signal representative of the temperature measured by the temperature sensor and configured to generate a code word indicative of the measured temperature and a type of the temperature sensor, the temperature sensor being selected from one of at least two different temperature sensor types.

Abstract: A method and a device for regulating the threshold voltage of a transistor is disclosed. The device includes a circuit configured for modifying a voltage applied at a bulk connection of the transistor such that the threshold voltage of the transistor is substantially temperature-independent at least in a first temperature range. In one embodiment, the device includes a memory device, and the transistor is a transistor of a sense amplifier of the memory device.

Abstract: The invention relates to a voltage regulating circuit arrangement for converting a first voltage (VEXT) applied to an input of said voltage regulating circuit arrangement into a second voltage (VBLH) that may be tapped at an output of said voltage regulating circuit arrangement, wherein, when said first voltage (VEXT) falls below a threshold value (VEXT_THRESHOLD), the first voltage (VEXT) applied to the input of said voltage regulating circuit arrangement is connected through to said output of said voltage regulating circuit arrangement.

Abstract: An oscillator circuit includes a capacitor device, a current source for supplying a current to the capacitor device, a reference voltage, and a control circuit. The reference voltage is a first input to a comparator. An output of the capacitor device and an output of the current source are a second input to the comparator. The control circuit resets the oscillator circuit when the first and second inputs to the comparator are equal.

Abstract: An integrated semiconductor memory can include a plurality of subcircuit blocks arranged on nonoverlapping area sections. The subcircuit blocks each have a block supply line and a block ground line, which supply individual switching elements of the subcircuit blocks with a voltage. Each block supply line and block ground line is connected to a chip supply line and a chip ground line, which run outside the area sections of the subcircuit blocks. At least one connection between the chip supply line and the block supply line of at least one subcircuit block or between the chip ground line and the block ground line of at least one subcircuit block can be isolated by a switching device. Furthermore, a method for reducing leakage currents in a semiconductor memory, which, depending on the operating state of the semiconductor memory, isolates or connects individual subcircuit blocks of the semiconductor memory from or to a voltage supply.

Abstract: The invention relates to a method for operating a driver device (1), and to a driver device (1), in particular for a semiconductor device, said driver device (1) comprising: a signal driver (6a) connected to a supply voltage (VDDQ), c h a r a c t e r i z e d i n t h a t the driver device (1) additionally comprises: means (5) for activating a further signal driver (6b) when the supply voltage (VDDQ) lies below a predetermined threshold value (VDDQthreshold, VDDQthreshold1).

Abstract: The invention relates to a system (1) comprising a first semiconductor device (2a), and a second semiconductor device (2b), wherein the first semiconductor device (2a) comprises a voltage supply means (3a), and wherein the voltage supply means (3a) of the first semiconductor device (2a) is connected to the second semiconductor device (2b), so that the voltage supply means (3a) of the first semiconductor device (2a) can provide a supply voltage for the second semiconductor device (2b).

Abstract: An integrated semiconductor memory can include a plurality of subcircuit blocks arranged on nonoverlapping area sections. The subcircuit blocks each have a block supply line and a block ground line, which supply individual switching elements of the subcircuit blocks with a voltage. Each block supply line and block ground line is connected to a chip supply line and a chip ground line, which run outside the area sections of the subcircuit blocks. At least one connection between the chip supply line and the block supply line of at least one subcircuit block or between the chip ground line and the block ground line of at least one subcircuit block can be isolated by a switching device. Furthermore, a method for reducing leakage currents in a semiconductor memory, which, depending on the operating state of the semiconductor memory, isolates or connects individual subcircuit blocks of the semiconductor memory from or to a voltage supply.

Abstract: An integrated dynamic memory contains a control circuit for controlling a refresh mode in which the memory cells undergo refreshing of their contents. A controllable frequency generator serves for setting a refresh frequency. A temperature sensor circuit detects a temperature of the memory and outputs a first reference value, and an externally writable circuit is provided for outputting a second reference value. The temperature sensor circuit and the externally writable circuit are alternatively connectible to the control input of the frequency generator for setting the refresh frequency. If the externally writable circuit has been written, the second reference value, which corresponds to a temperature, is fed to the frequency generator; otherwise, the first reference value is supplied. In this manner, users of the memory that are unable to measure temperature can expediently optimize the power consumption that is necessary for standby mode and reduce it at low temperatures.

Abstract: An electronic circuit for generating an output voltage has a defined temperature dependence, a bandgap circuit for generating a defined temperature-constant voltage and a temperature-dependent current with a defined temperature dependence, and a conversion circuit for generating the output voltage from the temperature-dependent current and the temperature-constant voltage. The conversion circuit has a first resistor at whose first terminal the temperature-constant voltage is applied, and whose second terminal is connected to a first terminal of a second resistor. The second terminal of the second resistor is connected to a supply voltage potential, and a first terminal of a third resistor is connected to the second terminal of the first resistor. The temperature-dependent current is supplied to a second terminal of the third resistor, and it being possible to tap the output voltage at the second terminal of the third resistor.

Abstract: The invention relates to a voltage regulating circuit arrangement (1, 101) for converting a first voltage (VEXT) applied to an input of said voltage regulating circuit arrangement (1, 101) into a second voltage (VBLH) that may be tapped at an output (10, 110) of said voltage regulating circuit arrangement (1, 101), wherein, when said first voltage (VEXT) falls below a threshold value (VEXT_THRESHOLD), the first voltage (VEXT) applied to the input of said voltage regulating circuit arrangement (1, 101) is connected through to said output (10, 110) of said voltage regulating circuit arrangement (1, 101).

Abstract: A method and an integrated circuit for boosting a voltage are disclosed. A two-stage charge pump is used and has switches and capacitors. Known charges pumps can be single-stage or multi-stage and can achieve only a doubling of the input voltage in practice, depending on the configuration of the switches and capacitors and whereby each stage is provided with a separate drive. An improved two-stage charge pump can triple the input voltage and is advantageously achieved. N-type field effect transistors that are embedded in the substrate of an integrated circuit are utilized as the switches. It is further provided that a second series pass transistor is driven at its bulk terminal and/or its gate by a capacitor and a level shifter. This advantageously obviates the need to expand the width of the additional series pass transistor.

Abstract: An integrated dynamic memory contains a control circuit for controlling a refresh mode in which the memory cells undergo refreshing of their contents. A controllable frequency generator serves for setting a refresh frequency. A temperature sensor circuit detects a temperature of the memory and outputs a first reference value, and an externally writable circuit is provided for outputting a second reference value. The temperature sensor circuit and the externally writable circuit are alternatively connectible to the control input of the frequency generator for setting the refresh frequency. If the externally writable circuit has been written, the second reference value, which corresponds to a temperature, is fed to the frequency generator; otherwise, the first reference value is supplied. In this manner, users of the memory that are unable to measure temperature can expediently optimize the power consumption that is necessary for standby mode and reduce it at low temperatures.