Abstract: A device including a first metal feature is disposed in a first insulating layer. A second metal feature is disposed in a second insulating layer and separated from the first metal feature by a portion of a first etch stop liner disposed between the first and the second insulating layers. The second metal feature is capacitively coupled to the first metal feature through the first etch stop liner.

Abstract: A device including a first metal feature is disposed in a first insulating layer. A second metal feature is disposed in a second insulating layer and separated from the first metal feature by a portion of a first etch stop liner disposed between the first and the second insulating layers. The second metal feature is capacitively coupled to the first metal feature through the first etch stop liner.

Abstract: A device including a first metal feature is disposed in a first insulating layer. A second metal feature is disposed in a second insulating layer and separated from the first metal feature by a portion of a first etch stop liner disposed between the first and the second insulating layers. The second metal feature is capacitively coupled to the first metal feature through the first etch stop liner.

Abstract: Disclosed herein are various methods of forming conductive structures, such as conductive lines and vias, using a dual metal hard mask integration technique. In one example, the method includes forming a first layer of insulating material, forming a first patterned metal hard mask layer above the first layer of insulating material, forming a second patterned metal hard mask layer above the first patterned metal hard mask layer, performing at least one etching process through both of the second patterned metal hard mask layer and the first patterned metal hard mask layer to define a trench in the first layer of insulating material and forming a conductive structure in the trench.

Abstract: A filter device has a compact filter made of a filter material that is wound spirally. A star filter that is made of a filter material that has folds arranged in a star shape surrounds the compact filter. The filter device has a cylindrical shape. A fluid to be filtered passes the compact filter in an axial direction and the star filter in a radial direction. The filter device is exchangeable and is mounted in a filter housing such that the compact filter and the star filter have a common raw side and a common clean side that are separated from each other.

Abstract: In a semiconductor device, through hole vias or through silicon vias (TSV) may be formed so as to include an efficient stress relaxation mechanism, for instance provided on the basis of a stress relaxation layer, in order to reduce or compensate for stress forces caused by a pronounced change in volume of the conductive fill materials of the through hole vias. In this manner, the high risk of creating cracks and delamination events in conventional semiconductor devices may be significantly reduced.

Abstract: Generally, the present disclosure is directed to forming conductive metal fill materials in replacement gate electrodes using reduced deposition temperatures. One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor layer, the sacrificial gate structure including a dummy gate electrode, and forming a gate cavity by removing at least the dummy gate electrode from above the semiconductor layer. The disclosed method further includes forming a work-function material of a replacement metal gate electrode in the gate cavity, and forming a conductive metal fill material in the gate cavity and above the work-function material, wherein forming the conductive metal fill material includes performing a material deposition process at a temperature below approximately 450° C.

Abstract: Disclosed herein are various methods of forming conductive structures, such as conductive lines and vias, using a dual metal hard mask integration technique. In one example, the method includes forming a first layer of insulating material, forming a first patterned metal hard mask layer above the first layer of insulating material, forming a second patterned metal hard mask layer above the first patterned metal hard mask layer, performing at least one etching process through both of the second patterned metal hard mask layer and the first patterned metal hard mask layer to define a trench in the first layer of insulating material and forming a conductive structure in the trench.

Abstract: The invention concerns a filter insert (1) that is provided as an exchangeable insert in an oil filter of an internal combustion engine, as well as a corresponding oil filter. The oil filter comprises a filter housing (3) separable along a separating plane (2) and the exchangeable filter insert (1). Two housing parts (4, 5) of the filter housing (3) are sealed relative one another along the separating plane (2) by means of a seal (6). The seal (6) is captively secured on the filter insert (1).

Abstract: Disclosed herein are various methods of filing voids in copper conductive structures on integrated circuit devices. In one example, the method includes the steps of forming a conductive copper structure in a layer of insulating material and performing an electroless deposition process to selectively form a fill layer comprised of a conductive material on the copper containing structure, the fill layer being adapted to at least partially fill any voids that may exist in the conductive copper structure.

Abstract: Integrated circuits and methods for fabricating an integrated circuit are provided. A conductive feature is formed in a semiconductor substrate. A layer of ULK or LK dielectric material is formed overlying the conductive feature. An opening having a sidewall surface is etched through the layer of ULK or LK dielectric material. Damage on the sidewall surface resulting from the etching is removed. An ULK or LK dielectric liner is formed overlying the sidewall surface. The ULK or LK dielectric liner along the bottom of the opening is removed to expose the conductive feature. The opening is filled with a metal fill material contacting the conductive feature.

Abstract: A filter device has a compact filter made of a filter material that is wound spirally. A star filter that is made of a filter material that has folds arranged in a star shape surrounds the compact filter. The filter device has a cylindrical shape. A fluid to be filtered passes the compact filter in an axial direction and the star filter in a radial direction. The filter device is exchangeable and is mounted in a filter housing such that the compact filter and the star filter have a common raw side and a common clean side that are separated from each other.

Abstract: In a semiconductor device, through hole vias or through silicon vias (TSV) may be formed so as to include an efficient stress relaxation mechanism, for instance provided on the basis of a stress relaxation layer, in order to reduce or compensate for stress forces caused by a pronounced change in volume of the conductive fill materials of the through hole vias. In this manner, the high risk of creating cracks and delamination events in conventional semiconductor devices may be significantly reduced.

Abstract: One embodiment of the present invention relates to a transistor that is at least partially formed in a semiconductor substrate having a surface. In particular, the transistor includes a first source/drain region, a second source/drain region, a channel region connecting said first and second source/drain regions. Said channel region is disposed in said semiconductor substrate. A channel direction is defined by a line connecting said first and said second source/drain regions. A gate groove is formed in said semiconductor substrate. Said gate groove is formed adjacent to said channel region. Said gate groove includes an upper portion and a lower portion, said upper portion being adjacent to said lower portion, and a gate dielectric layer disposed between said channel region and said gate groove.

Abstract: The present invention provides a fabrication method for an integrated circuit structure comprising the steps of forming a electrode layer stack (5, 6?, 7?, 8?) by sequentially depositing a polysilicon layer (5) on a gate dielectric layer (9); a contact layer (6?) composed of Ti on the polysilicon layer (5); a barrier layer (7?) composed of WN on the contact layer (6?); and a metal layer (8?) composed of W on the barrier layer (7?); wherein steps iii) and iv) are carried out as PVD steps using krypton and/or xenon as sputtering gas; and annealing the layer stack (5, 6?, 7?, 8?) in a thermal step in the temperature range of between 600 and 950° C.

Abstract: The present invention provides a manufacturing method for an integrated semiconductor contact structure having an improved Aluminum fill comprising the steps of: forming contact holes in an insulation layer provided on a wafer, said contact holes having a respective bottom and respective sidewalls, said bottoms including a respective conductive area; introducing said wafer into a first PVD deposition chamber, said first PVD deposition chamber including a wafer bias means; and cold depositing a first Aluminum layer on the wafer in said first PVD deposition chamber, said first Aluminum layer covering said bottoms and said sidewalls of said contact holes and forming a seed layer; wherein during said step of cold depositing said first Aluminum layer on the wafer in said first PVD deposition chamber said wafer bias means is set to a bias in the range between 20 W and 700 W or ?50 V to ?800 V.

Abstract: One embodiment of the present invention relates to a transistor that is at least partially formed in a semiconductor substrate having a surface. In particular, the transistor includes a first source/drain region, a second source/drain region, a channel region connecting said first and second source/drain regions. Said channel region is disposed in said semiconductor substrate. A channel direction is defined by a line connecting said first and said second source/drain regions. A gate groove is formed in said semiconductor substrate. Said gate groove is formed adjacent to said channel region. Said gate groove includes an upper portion and a lower portion, said upper portion being adjacent to said lower portion, and a gate dielectric layer disposed between said channel region and said gate groove.

Abstract: A process for producing aluminum-filled contact holes in a wafer is disclosed. The process uses a coating installation that includes a plurality of vacuum-processing chambers that are coupled to one another via at least one transfer chamber with an associated handler for transferring the wafers. The preferred process including forming the contact holes and depositing a barrier layer. The wafer is cooled to ambient temperature. A cold aluminum PVD coating process can then be carried out in a PVD-aluminum ESC chamber. After the wafer is heated (e.g., to a temperature of less than about 450° C.), a hot aluminum PVD deposition process is carried out in the PVD-aluminum ESC chamber.

Abstract: A method for providing whisker-free aluminum metal lines or aluminum alloy lines in integrated circuits includes the following steps: providing a substrate; providing a whisker-containing layer made of aluminum metal or an aluminum alloy on the substrate; back-etching and/or resputtering the whisker-containing layer such that the whiskers are essentially removed; and structuring the whisker-free layer into the lines.

Abstract: The invention relates to a method of manufacturing a semiconductor device, in which a substrate is provided, a dielectric layer is formed on top of the substrate, an amorphous semiconductor layer id deposited on top of the dielectric layer, the amorphous semiconductor layer is doped, and a high temperature step to the amorphous layer is applied to form a crystallized layer out of the amorphous semiconductor.