Patents by Inventor Jens-Peer Stengl

Jens-Peer Stengl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6271562
    Abstract: A power semiconductor component that can be controlled by a field effect has a multiplicity of parallel-connected individual components disposed in cells, the cells are disposed tightly packed on a relatively small space in a cell array. Parallel-connected source zones of the cells have shadowed regions that in each case reduce an effective W/L channel ratio in the cells containing the shadowed regions. The invention has the advantage that because of the provision of the shadowed regions inside the source zones that are preferably undoped or at least doped much weaker than the source zones, the critical regions in the cell array with the highest current density are specifically moderated. Thus the current density in the current-carrying filament of the cell is more homogeneously distributed. This measure renders it possible to reduce the cell grid spacing of the cells in the cell array, or to reduce the forward resistance per unit area, and this leads simultaneously to a reduction in the power loss.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: August 7, 2001
    Assignee: Infineon Technologies AG
    Inventors: Gerald Deboy, Jens-Peer Stengl, Jenoe Tihanyi, Heimo Graf
  • Patent number: 6037631
    Abstract: A semiconductor component having a high-voltage endurance edge structure in which a multiplicity of parallel-connected individual components are disposed in a multiplicity of cells of a cell array. In an edge region, the semiconductor component has cells with shaded source zone regions. During commutation of the power semiconductor component, the shaded source zone regions suppress the switching on of a parasitic bipolar transistor caused by the disproportionately large reverse flow current density. Moreover, an edge structure having shaded source zone regions can be produced very easily in technological terms, in particular in the case of self-adjusting processes, and can thus be produced cost-effectively.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: March 14, 2000
    Assignee: Siemens Aktiengesellschaft
    Inventors: Gerald Deboy, Helmut Gassel, Jens-Peer Stengl
  • Patent number: 5726478
    Abstract: An integrated power semiconductor component includes a substrate of a first conduction type. At least one first region of a second conduction type is embedded in the substrate and at least one second region of the second conduction type is embedded in the substrate. A substrate contact supplies a supply voltage. Contact-making semiconductor components are embedded in the first region and in the second region. At least a portion of the semiconductor components in the first region control at least a portion of the semiconductor components in the second region. A third region of the second conduction type is disposed between the first region and the second region, and the first region and the third region are at different potentials.
    Type: Grant
    Filed: December 19, 1996
    Date of Patent: March 10, 1998
    Assignee: Siemens Aktiengesellschaft
    Inventors: Josef-Matthias Gantioler, Ludwig Leipold, Rainald Sander, Jens-Peer Stengl, Jenoe Tihanyi
  • Patent number: 4459498
    Abstract: Switch with at least two series-connected MOS-FETs has a drain terminal of a preceding MOS-FET connected to a source terminal of a succeeding MOS-FET the MOS-FETs having respective control terminals connectible to a control voltage. The control terminal of the preceding MOS-FET is directly connected to a terminal of the control voltage source. The control terminal of the succeeding MOS-FET is connected to the control terminal of the respective preceding MOS-FET via a diode poled in forward direction with respect to the control voltage source. A resistor is connected between the control terminal and the source terminal of the succeeding MOS-FET.
    Type: Grant
    Filed: June 26, 1981
    Date of Patent: July 10, 1984
    Assignee: Siemens Aktiengesellschaft
    Inventors: Jens-Peer Stengl, Hartmut Thomas, Jeno Tihanyi