Patents by Inventor Jens Polney
Jens Polney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230215828Abstract: Layouts for data pads on a semiconductor die are disclosed. An apparatus may include circuits, a first edge, a second edge perpendicular to the first edge, a third edge opposite the first edge, and a fourth edge opposite the second edge. The apparatus may also include data pads variously electrically coupled to the circuits. The data pads may include a data pad positioned a first distance from the first edge and a second distance from the second edge. The apparatus may also include dummy data pads electrically isolated from the circuits. The dummy data pads may include a dummy data pad positioned substantially the first distance from the first edge and substantially the second distance from the fourth edge. Associated systems and methods are also disclosed.Type: ApplicationFiled: August 31, 2022Publication date: July 6, 2023Inventors: Andreas Kuesel, Takamasa Suzuki, Jens Polney, Seiji Narui, Shiro Uchiyama
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Patent number: 10943627Abstract: Apparatuses and methods for providing internal clock signals of different clock frequencies in a semiconductor device are described in the present application. An example apparatus includes a read command buffer and a read data output circuit. The read command. buffer buffers a read command responsive to a first clock signal and provides the read command responsive to a second clock signal. The read data output circuit receives a plurality of bits of data in parallel when activated by the read command from the read command buffer, and provides the plurality of bits of data serially responsive to input/output (IO) clock signals. A data clock timing circuit provides the IO clock signals having a first clock frequency in a first mode and having a second clock frequency in a second mode, and further provides the second clock signal having the first clock frequency in the first and second modes.Type: GrantFiled: April 9, 2019Date of Patent: March 9, 2021Assignee: Micron Technology, Inc.Inventor: Jens Polney
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Publication number: 20190237117Abstract: Apparatuses and methods for providing internal clock signals of different clock frequencies in a semiconductor device are described in the present application. An example apparatus includes a read command buffer and a read data output circuit. The read command. buffer buffers a read command responsive to a first clock signal and provides the read command responsive to a second clock signal. The read data output circuit receives a plurality of bits of data in parallel when activated by the read command from the read command buffer, and provides the plurality of bits of data serially responsive to input/output (IO) clock signals. A data clock timing circuit provides the IO clock signals having a first clock frequency in a first mode and having a second clock frequency in a second mode, and further provides the second clock signal having the first clock frequency in the first and second modes.Type: ApplicationFiled: April 9, 2019Publication date: August 1, 2019Applicant: MICRON TECHNOLOGY, INC.Inventor: Jens Polney
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Patent number: 10297298Abstract: Apparatuses and methods for providing internal clock signals of different clock frequencies in a semiconductor device are described in the present application. An example apparatus includes a read command buffer and a read data output circuit. The read command buffer buffers a read command responsive to a first clock signal and provides the read command responsive to a second clock signal. The read data output circuit receives a plurality of bits of data in parallel when activated by the read command from the read command buffer, and provides the plurality of bits of data serially responsive to input/output (IO) clock signals. A data clock timing circuit provides the IO clock signals having a first clock frequency in a first mode and having a second clock frequency in a second mode, and further provides the second clock signal having the first clock frequency in the first and second modes.Type: GrantFiled: October 11, 2017Date of Patent: May 21, 2019Assignee: Micron Technology, Inc.Inventor: Jens Polney
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Publication number: 20180204608Abstract: Apparatuses and methods for providing internal clock signals of different clock frequencies in a semiconductor device are described in the present application. An example apparatus includes a read command buffer and a read data output circuit. The read command buffer buffers a read command responsive to a first clock signal and provides the read command responsive to a second clock signal. The read data output circuit receives a plurality of bits of data in parallel when activated by the read command from the read command buffer, and provides the plurality of bits of data serially responsive to input/output (IO) clock signals. A data clock timing circuit provides the IO clock signals having a first clock frequency in a first mode and having a second clock frequency in a second mode, and further provides the second clock signal having the first clock frequency in the first and second modes.Type: ApplicationFiled: October 11, 2017Publication date: July 19, 2018Applicant: Micron Technology, Inc.Inventor: Jens Polney
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Patent number: 9818462Abstract: Apparatuses and methods for providing internal clock signals of different clock frequencies in a semiconductor device are described in the present application. An example apparatus includes a read command buffer and a read data output circuit. The read command buffer buffers a read command responsive to a first clock signal and provides the read command responsive to a second clock signal. The read data output circuit receives a plurality of bits of data in parallel when activated by the read command from the read command buffer, and provides the plurality of bits of data serially responsive to input/output (IO) clock signals. A data clock timing circuit provides the IO clock signals having a first clock frequency in a first mode and having a second clock frequency in a second mode, and further provides the second clock signal having the first clock frequency in the first and second modes.Type: GrantFiled: January 19, 2017Date of Patent: November 14, 2017Assignee: Micron Technology, Inc.Inventor: Jens Polney
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Patent number: 7573760Abstract: An integrated circuit comprises a sampling circuit arranged at a data output of an operating section and operated by sampling edges, data packets appearing at the data output in response to a sequence of request commands, and a control section configured to produce the sampling edges, the control section comprising at least two transmission branches each comprising a copy of the operating section. Pulse trains are applied to the transmission branches which have the same waveform as the sequence of request commands and are delayed relative to one another, wherein the first pulse train is contemporaneous with the sequence of request commands. The sampling edges are produced from leading edges of the pulse trains which appear at the outputs of the transmission branches.Type: GrantFiled: September 12, 2007Date of Patent: August 11, 2009Assignee: Qimonda AGInventors: Christian Sichert, Rainer Bartenschlager, Franz Freimuth, Jens Polney
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Patent number: 7554875Abstract: A bus structure comprises a plurality of driver circuits, each driver circuit comprising an input for a first signal and a terminal for an output signal wherein each driver circuit is capable of providing the output signal at the terminal upon receipt of the first signal, a parallel bus comprising a plurality of output signal lines at a receiving end, being connectable to a target component, each of the signal lines extending at least from the receiving end to the terminal of a different one of the plurality of driver circuits, such that a length of the output signal line between the receiving end and the respective driver circuits decreases in a connection order among the plurality of driver circuits, and a signal line coupled to each of the inputs of the driver circuits in the connection order.Type: GrantFiled: January 31, 2007Date of Patent: June 30, 2009Assignee: Qimonda AGInventors: Christian Sichert, Rainer Bartenschlager, Jens Polney
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Publication number: 20080181044Abstract: A bus structure comprises a plurality of driver circuits, each driver circuit comprising an input for a first signal and a terminal for an output signal wherein each driver circuit is capable of providing the output signal at the terminal upon receipt of the first signal, a parallel bus comprising a plurality of output signal lines at a receiving end, being connectable to a target component, each of the signal lines extending at least from the receiving end to the terminal of a different one of the plurality of driver circuits, such that a length of the output signal line between the receiving end and the respective driver circuits decreases in a connection order among the plurality of driver circuits, and a signal line coupled to each of the inputs of the driver circuits in the connection order.Type: ApplicationFiled: January 31, 2007Publication date: July 31, 2008Inventors: Christian Sichert, Rainer Bartenschlager, Jens Polney
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Publication number: 20080061852Abstract: An integrated circuit comprises a sampling circuit arranged at a data output of an operating section and operated by sampling edges, data packets appearing at the data output in response to a sequence of request commands, and a control section configured to produce the sampling edges, the control section comprising at least two transmission branches each comprising a copy of the operating section. Pulse trains are applied to the transmission branches which have the same waveform as the sequence of request commands and are delayed relative to one another, wherein the first pulse train is contemporaneous with the sequence of request commands. The sampling edges are produced from leading edges of the pulse trains which appear at the outputs of the transmission branches.Type: ApplicationFiled: September 12, 2007Publication date: March 13, 2008Inventors: Christian Sichert, Rainer Bartenschlager, Franz Freimuth, Jens Polney
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Patent number: 7123523Abstract: An integrated circuit, in particular an integrated memory circuit, has an input circuit for the purpose of receiving a signal. The input circuit has an activation input for an activation signal in order to activate the input circuit, in a manner dependent on the activation signal, for the purpose of receiving signals.Type: GrantFiled: September 25, 2003Date of Patent: October 17, 2006Assignee: Infineon Technologies AGInventors: Andre Schäfer, Kazimierz Szczypinski, Jens Polney
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Publication number: 20060133172Abstract: The invention proposes an apparatus for writing to and/or reading from a memory cell in a semiconductor memory having a selection transistor and a storage capacitor, where the apparatus has a device which is used to influence a threshold voltage for the selection transistor contrary to the influence of an ambient temperature. The invention also proposes a method for writing to and/or reading from a memory cell in a semiconductor memory having a selection transistor and a storage capacitor, where the method comprises the following method steps: a) an ambient temperature for the memory cell is ascertained, and b) an electrical voltage is applied to a substrate well in the selection transistor as a function of the ascertained ambient temperature such that a threshold voltage for the selection transistor is influenced contrary to the influence of an ambient temperature.Type: ApplicationFiled: November 18, 2005Publication date: June 22, 2006Inventors: Florian Schnabel, Jens Polney
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Patent number: 6977862Abstract: Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a memory circuit are provided. One embodiment provides a method for addressing memory areas in a memory circuit with successive addresses, with either a regular memory area or a redundant memory area being addressed depending on the address, with an inactive state of a deactivation signal being set when addressing the regular memory area, which inactive state allows the addressing of the regular memory area, with the addressing of the regular memory area being blocked on the basis of an active state of the deactivation signal when addressing the redundant memory area, wherein a change is made from the active state of the deactivation signal to the inactive state of the deactivation signal before the application of the next address for addressing one of the memory areas.Type: GrantFiled: August 18, 2004Date of Patent: December 20, 2005Assignee: Infineon Technologies AGInventors: Florian Schnabel, Jens Polney
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Publication number: 20050117416Abstract: Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a memory circuit are provided. One embodiment provides a method for addressing memory areas in a memory circuit with successive addresses, with either a regular memory area or a redundant memory area being addressed depending on the address, with an inactive state of a deactivation signal being set when addressing the regular memory area, which inactive state allows the addressing of the regular memory area, with the addressing of the regular memory area being blocked on the basis of an active state of the deactivation signal when addressing the redundant memory area, wherein a change is made from the active state of the deactivation signal to the inactive state of the deactivation signal before the application of the next address for addressing one of the memory areas.Type: ApplicationFiled: August 18, 2004Publication date: June 2, 2005Inventors: Florian Schnabel, Jens Polney
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Publication number: 20040056693Abstract: An integrated circuit, in particular an integrated memory circuit, has an input circuit for the purpose of receiving a signal. The input circuit has an activation input for an activation signal in order to activate the input circuit, in a manner dependent on the activation signal, for the purpose of receiving signals.Type: ApplicationFiled: September 25, 2003Publication date: March 25, 2004Inventors: Andre Schafer, Kazimierz Szczypinski, Jens Polney
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Patent number: 6525597Abstract: In integrated circuits with internally generated supply voltages, during the run-up of the internal voltage generators, unintentionally high currents can arise through switching stages connected to the internal supply voltage. A control circuit provides for the initialization of the switching stages during power-up. The control circuit contains an inverter that, in signal terms, can be driven by a precharge signal and, on the supply voltage side, is connected to the internal supply voltage via respective transistors. During power-up, the transistors are switched off and then switched on. The precharge signal is forwarded to the switching stage via a further inverter.Type: GrantFiled: November 8, 2001Date of Patent: February 25, 2003Assignee: Infineon Technologies AGInventor: Jens Polney
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Patent number: 6504359Abstract: A method for testing electronic components includes the step of outputting test output data for the tested electronic components on a test board without activating individual scan lines or individual scan signals. Starting from a first activated electronic component successively the following electronic components are activated one after another by passing an activation signal from electronic component to electronic component. A device for testing electronic components is also provided.Type: GrantFiled: January 24, 2001Date of Patent: January 7, 2003Assignee: Infineon Technologies AGInventor: Jens Polney
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Publication number: 20020063595Abstract: In integrated circuits with internally generated supply voltages, during the run-up of the internal voltage generators, unintentionally high currents can arise through switching stages connected to the internal supply voltage. A control circuit provides for the initialization of the switching stages during power-up. The control circuit contains an inverter that, in signal terms, can be driven by a precharge signal and, on the supply voltage side, is connected to the internal supply voltage via respective transistors. During power-up, the transistors are switched off and then switched on. The precharge signal is forwarded to the switching stage via a further inverter.Type: ApplicationFiled: November 8, 2001Publication date: May 30, 2002Inventor: Jens Polney
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Patent number: 6363017Abstract: In a random access memory, a sequence of selection signals for a combined multi-memory operating functionality is supplied on control lines which connect the control logic to each memory cell in a cell field when the memory is in a combined multi-memory operating mode, and a sequence of selection signals for the write enable functionality is supplied when the memory is in the single-memory operating mode.Type: GrantFiled: January 19, 2001Date of Patent: March 26, 2002Assignee: Infineon Technologies AGInventor: Jens Polney
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Publication number: 20010019277Abstract: A method for testing electronic components includes the step of outputting test output data for the tested electronic components on a test board without activating individual scan lines or individual scan signals. Starting from a first activated electronic component successively the following electronic components are activated one after another by passing an activation signal from electronic component to electronic component. A device for testing electronic components is also provided.Type: ApplicationFiled: January 24, 2001Publication date: September 6, 2001Inventor: Jens Polney