Abstract: In sophisticated semiconductor devices, electronic fuses may be provided in the metallization system, wherein a superior two-dimensional configuration of the metal line, for instance as a helix-like configuration, may provide superior thermal conditions in a central line portion, which in turn may result in a more pronounced electromigration effect for a given programming current. Consequently, the size of the electronic fuse, at least in one lateral direction, and also the width of corresponding transistors connected to the electronic fuse, may be reduced.

Abstract: An approach is provided for semiconductor devices including an anti-fuse structure. The semiconductor device includes a first metallization layer including a first portion of a first electrode and a second electrode, the second electrode being formed in a substantially axial plane surrounding the first portion of the first electrode, with a dielectric material in between the two electrodes. An ILD is formed over the first metallization layer, a second metallization layer including a second portion of the first electrode is formed over the ILD, and at least one via is formed through the ILD, electrically connecting the first and second portions of the first electrode. Breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure.

Abstract: Metal fuses in semiconductor devices may be formed on the basis of additional mechanisms for obtaining superior electromigration in the fuse bodies. To this end, the compressive stress caused by the current-induced metal diffusion may be restricted or reduced in the fuse body, for instance, by providing a stress buffer region and/or by providing a dedicated metal agglomeration region. The concept may be applied to the metallization system and may also be used in the device level, when fabricating the metal fuse in combination with high-k metal gate electrode structures.

Abstract: Disclosed herein is a metal e-fuse device that employs an intermetallic compound programming mechanism and various methods of making such an e-fuse device. In one example, a device disclosed herein includes a first metal line, a second metal line and a fuse element that is positioned between and conductively coupled to each of the first and second metal lines, wherein the fuse element is adapted to be blown by passing a programming current therethrough, and wherein the fuse element is comprised of a material that is different from a material of construction of at least one of the first and second metal lines.

Abstract: Metal fuses in semiconductor devices may be formed on the basis of additional mechanisms for obtaining superior electromigration in the fuse bodies. To this end, the compressive stress caused by the current-induced metal diffusion may be restricted or reduced in the fuse body, for instance, by providing a stress buffer region and/or by providing a dedicated metal agglomeration region. The concept may be applied to the metallization system and may also be used in the device level, when fabricating the metal fuse in combination with high-k metal gate electrode structures.

Abstract: An approach is provided for semiconductor devices including an anti-fuse structure. The semiconductor device includes a first metallization layer including a first portion of a first electrode and a second electrode, the second electrode being formed in a substantially axial plane surrounding the first portion of the first electrode, with a dielectric material in between the two electrodes. An ILD is formed over the first metallization layer, a second metallization layer including a second portion of the first electrode is formed over the ILD, and at least one via is formed through the ILD, electrically connecting the first and second portions of the first electrode. Breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure.

Abstract: An approach is provided for semiconductor devices including an anti-fuse structure. The semiconductor device includes a first metallization layer including a first portion of a first electrode and a second electrode, the second electrode being formed in a substantially axial plane surrounding the first portion of the first electrode, with a dielectric material in between the two electrodes. An ILD is formed over the first metallization layer, a second metallization layer including a second portion of the first electrode is formed over the ILD, and at least one via is formed through the ILD, electrically connecting the first and second portions of the first electrode. Breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure.

Abstract: Disclosed herein is a metal e-fuse device that employs an intermetallic compound programing mechanism and various methods of making such an e-fuse device. In one example, a device disclosed herein includes a first metal line, a second metal line and a fuse element that is positioned between and conductively coupled to each of the first and second metal lines, wherein the fuse element is adapted to be blown by passing a programming current therethrough, and wherein the fuse element is comprised of a material that is different from a material of construction of at least one of the first and second metal lines.

Abstract: An approach is provided for semiconductor devices including an anti-fuse structure. The semiconductor device includes a first metallization layer including a first portion of a first electrode and a second electrode, the second electrode being formed in a substantially axial plane surrounding the first portion of the first electrode, with a dielectric material in between the two electrodes. An ILD is formed over the first metallization layer, a second metallization layer including a second portion of the first electrode is formed over the ILD, and at least one via is formed through the ILD, electrically connecting the first and second portions of the first electrode. Breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure.

Abstract: In sophisticated integrated circuits, an electronic fuse may be formed such that an increased sensitivity to electromigration may be accomplished by including at least one region of increased current density. This may be accomplished by forming a corresponding fuse region as a non-linear configuration, wherein at corresponding connection portions of linear segments, the desired enhanced current crowding may occur during the application of the programming voltage. Hence, increased reliability and more space-efficient layout of the electronic fuses may be accomplished.

Abstract: In sophisticated semiconductor devices, electronic fuses may be provided in the metallization system, wherein a superior two-dimensional configuration of the metal line, for instance as a helix-like configuration, may provide superior thermal conditions in a central line portion, which in turn may result in a more pronounced electromigration effect for a given programming current. Consequently, the size of the electronic fuse, at least in one lateral direction, and also the width of corresponding transistors connected to the electronic fuse, may be reduced.

Abstract: Metal fuses in semiconductor devices may be formed on the basis of additional mechanisms for obtaining superior electromigration in the fuse bodies. To this end, the compressive stress caused by the current-induced metal diffusion may be restricted or reduced in the fuse body, for instance, by providing a stress buffer region and/or by providing a dedicated metal agglomeration region. The concept may be applied to the metallization system and may also be used in the device level, when fabricating the metal fuse in combination with high-k metal gate electrode structures.

Abstract: In sophisticated integrated circuits, an electronic fuse may be formed such that an increased sensitivity to electromigration may be accomplished by including at least one region of increased current density. This may be accomplished by forming a corresponding fuse region as a non-linear configuration, wherein at corresponding connection portions of linear segments, the desired enhanced current crowding may occur during the application of the programming voltage. Hence, increased reliability and more space-efficient layout of the electronic fuses may be accomplished.