Abstract: A ring oscillator-based analog-to-digital converter (ADC). The ring oscillator-based ADC includes a ring oscillator and a transition detector. The ring oscillator may include a set of inverters coupled in a ring wherein an output of an inverter is coupled to an input of a successive inverter in the ring. The transition detector is configured to detect transitions of outputs of the inverters by comparing outputs of two separate inverters at two consecutive time instances. The transition detector may include two sets of registers configured to store outputs of the set of inverters at two consecutive time instances, respectively, and a set of comparators configured to compare the outputs stored in the two sets of registers. Each comparator may be configured to compare an output of one inverter at a first time instance and an output of another inverter at a second time instance.

Abstract: A voltage-controlled ring oscillator (VCRO) and a VCRO-based sigma delta modulator having capability of enabling and disabling the VCRO cells. A VCRO includes a plurality of inverters coupled in a ring and a transition detector. The transition detector detects a transition of a first inverter and sends a control signal to enable a second inverter if the transition of the first inverter is detected. The transition detector may include a comparator configured to compare an input and an output of an inverter(s) to detect the transition of the first inverter and a latch configured to hold the control signal until it is reset.

Abstract: A ring oscillator-based analog-to-digital converter (ADC). The ring oscillator-based ADC includes a ring oscillator and a transition detector. The ring oscillator may include a set of inverters coupled in a ring wherein an output of an inverter is coupled to an input of a successive inverter in the ring. The transition detector is configured to detect transitions of outputs of the inverters by comparing outputs of two separate inverters at two consecutive time instances. The transition detector may include two sets of registers configured to store outputs of the set of inverters at two consecutive time instances, respectively, and a set of comparators configured to compare the outputs stored in the two sets of registers. Each comparator may be configured to compare an output of one inverter at a first time instance and an output of another inverter at a second time instance.

Abstract: A voltage-controlled ring oscillator (VCRO) and a VCRO-based sigma delta modulator having capability of enabling and disabling the VCRO cells. A VCRO includes a plurality of inverters coupled in a ring and a transition detector. The transition detector detects a transition of a first inverter and sends a control signal to enable a second inverter if the transition of the first inverter is detected. The transition detector may include a comparator configured to compare an input and an output of an inverter(s) to detect the transition of the first inverter and a latch configured to hold the control signal until it is reset.

Abstract: A clock configuration for driving switched op-amp circuits operated in opposite phases is presented in which a common off-phase of variable length is inserted between the on-phases of the individual operational amplifiers. The length of the off-phase can be adapted to the transient response of the operational amplifiers used. The clock configuration according to the invention can be used for further reducing the power consumption of switched op-amp circuits.

Abstract: An amplifier or filter circuit in switched capacitor circuit logic, comprising an amplifier or filter circuit in switched capacitor circuit logic with a switchable operation amplifier as an input stage of a switched opamp filter or amplifier circuit.

Abstract: A circuit configuration for providing a capacitance includes short-channel MOS transistors that are reverse-connected in series or in parallel, and that have the same channel type. When the short-channel MOS transistors are operated exclusively in the depletion mode in the required voltage range, the useful capacitance is increased, because of intrinsic capacitances, as compared with circuit configurations having conventional long-channel MOS transistors. These circuits greatly reduce the area taken up and reduce the costs.

Abstract: A switchable operational amplifier is presented for switched op amp technology, in which the current through the pre-stage is reduced during the off phase of the switching clock pulse. In this way, power consumption can be reduced. During the off phase of the switching clock pulse, the current can either be reduced or switched off completely.

Abstract: A circuit configuration for providing a capacitance includes short-channel MOS transistors that are reverse-connected in series or in parallel, and that have the same channel type. When the short-channel MOS transistors are operated exclusively in the depletion mode in the required voltage range, the useful capacitance is increased, because of intrinsic capacitances, as compared with circuit configurations having conventional long-channel MOS transistors. These circuits greatly reduce the area taken up and reduce the costs.

Abstract: A clock configuration for driving switched op-amp circuits operated in opposite phases is presented in which a common off-phase of variable length is inserted between the on-phases of the individual operational amplifiers. The length of the off-phase can be adapted to the transient response of the operational amplifiers used. The clock configuration according to the invention can be used for further reducing the power consumption of switched op-amp circuits.

Abstract: A switchable operational amplifier is presented for switched op amp technology, in which the current through the pre-stage is reduced during the off phase of the switching clock pulse. In this way, power consumption can be reduced. During the off phase of the switching clock pulse, the current can either be reduced or switched off completely.

Abstract: A digital-analog converter having high linearity is based on two sigma-delta modulators of second order which are fed back in a cascaded fashion and via differentiators. The first modulator has a quantizer with only three stages, an output signal of which delivers an analog output signal via a three-stage digital-analog converter and a low-pass filter. The particularly high linearity, the good stability and the relatively large bandwidth with reference to clock frequency are advantages of the digital-analog converter.

Abstract: A fully differential resistor-string digital-to-analog converter wherein a resistor network having half the number of resistors of an otherwise standard digital-to-analog convertor of this type is enabled with the assistance of a first decoder, a second decoder and a subtraction unit thus reducing the required chip area and the overall switching time.