Abstract: A first substrate 2002 has a calibration pattern applied to a first plurality of fields 2004 by a lithographic apparatus. Further substrates 2006, 2010 have calibration patterns applied to further pluralities of fields 2008, 2012. The different pluralities of fields have different sizes and/or shapes and/or positions. Calibration measurements are performed on the patterned substrates 2002, 2006, 2010 and used to obtain corrections for use in controlling the apparatus when applying product patterns to subsequent substrates. Measurement data representing the performance of the apparatus on fields of two or more different dimensions (fields 2004, 2008, 2012 in this example) is gathered together in a database 2013 and used to synthesize the information needed to calibrate the apparatus for a new size. Calibration data is also obtained for different scan and step directions.

Abstract: A first substrate 2002 has a calibration pattern applied to a first plurality of fields 2004 by a lithographic apparatus. Further substrates 2006, 2010 have calibration patterns applied to further pluralities of fields 2008, 2012. The different pluralities of fields have different sizes and/or shapes and/or positions. Calibration measurements are performed on the patterned substrates 2002, 2006, 2010 and used to obtain corrections for use in controlling the apparatus when applying product patterns to subsequent substrates. Measurement data representing the performance of the apparatus on fields of two or more different dimensions (fields 2004, 2008, 2012 in this example) is gathered together in a database 2013 and used to synthesize the information needed to calibrate the apparatus for a new size. Calibration data is also obtained for different scan and step directions.

Abstract: A first substrate (2002) has a calibration pattern applied to a first plurality of fields (2004) by a lithographic apparatus. Further substrates (2006, 2010) have calibration patterns applied to further pluralities of fields (2008, 2012). The different pluralities of fields have different sizes and/or shapes and/or positions. Calibration measurements are performed on the patterned substrates (2002, 2006, 2010) and used to obtain corrections for use in controlling the apparatus when applying product patterns to subsequent substrates. Measurement data representing the performance of the apparatus on fields of two or more different dimensions (2004, 2008, 2012) is gathered together in a database (2013) and used to synthesize the information needed to calibrate the apparatus for a new size. Calibration data is also obtained for different scan and step directions.

Abstract: A first substrate (2002) has a calibration pattern applied to a first plurality of fields (2004) by a lithographic apparatus. Further substrates (2006, 2010) have calibration patterns applied to further pluralities of fields (2008, 2012). The different pluralities of fields have different sizes and/or shapes and/or positions. Calibration measurements are performed on the patterned substrates (2002, 2006, 2010) and used to obtain corrections for use in controlling the apparatus when applying product patterns to subsequent substrates. Measurement data representing the performance of the apparatus on fields of two or more different dimensions (2004, 2008, 2012) is gathered together in a database (2013) and used to synthesize the information needed to calibrate the apparatus for a new size. Calibration data is also obtained for different scan and step directions.

Abstract: A lithography system configured to apply a pattern to a substrate, the system including a lithography apparatus configured to expose a layer of the substrate according to the pattern, and a machine learning controller configured to control the lithography system to optimize a property of the pattern, the machine learning controller configured to be trained on the basis of a property measured by a metrology unit configured to measure the property of the exposed pattern in the layer and/or a property associated with exposing the pattern onto the substrate, and to correct lithography system drift by adjusting one or more selected from: the lithography apparatus, a track unit configured to apply the layer on the substrate for lithographic exposure, and/or a control unit configured to control an automatic substrate flow among the track unit, the lithography apparatus, and the metrology unit.

Abstract: A lithography system configured to apply a pattern to a substrate, the system including a lithography apparatus configured to expose a layer of the substrate according to the pattern, and a machine learning controller configured to control the lithography system to optimize a property of the pattern, the machine learning controller configured to be trained on the basis of a property measured by a metrology unit configured to measure the property of the exposed pattern in the layer and/or a property associated with exposing the pattern onto the substrate, and to correct lithography system drift by adjusting one or more selected from: the lithography apparatus, a track unit configured to apply the layer on the substrate for lithographic exposure, and/or a control unit configured to control an automatic substrate flow among the track unit, the lithography apparatus, and the metrology unit.

Abstract: Methods and apparatus of manufacturing a semiconductor device are provided. Embodiments regard producing a first pattern in a first layer of a semiconductor substrate, producing a second pattern in a second layer of the semiconductor substrate, and matching the first pattern and the second pattern. The matching includes determining a mismatch between the first pattern and the second pattern that would occur without the matching and precorrecting the mismatch in the first layer.

Abstract: An arrangement for transferring information/structures to wafers uses a stamp on which the information/structures to be transferred have been applied as elevated structures. The wafer is fixed on a chuck and is provided with a plastically deformable auxiliary patterning layer. In various implementations, the dimensions of the stamp approximately correspond to those of the wafer, the stamp is provided with the elevated structures essentially over the whole area, and/or the stamp and the wafer are in each case provided with mutually assigned pairs of alignment marks in such a way that the stamp can be positioned in a predetermined position on the wafer by means of an infrared positioning system and can be pressed into the plastically deformable auxiliary patterning layer.

Abstract: A wafer exposure device includes a wafer stage. An optical exposure system exposes a wafer on the wafer stage. A sensor block measures a distance to a wafer provided on the wafer stage. The sensor block includes a plurality of height level sensors. Each height level sensor measures and outputs height level values. The wafer exposure device compares with one another the measured height level values outputted by respective height level sensors. The wafer exposure device calculates individual sensor position offset values to be attributed to the individual height level sensors. The wafer exposure device corrects the measured height level values output by the respective height level sensors using the calculated sensor position offset values of the respective height level sensor.

Abstract: The mutually associated structure patterns, which are provided on one mask, or a plurality of masks for a double or multiple exposure can be received by the mask substrate holder. The mask substrate holder has two receiving stations one for each of the masks. Alternatively, both structure patterns for the double exposure are formed on one mask. The substrate holder has one receiving station. The substrate holder, is displaced from the section including first structure pattern to the second, between the two exposure operations, without the masks having to be loaded or unloaded, and realigned.

Abstract: Described are systems and methods for orienting a semiconductor wafer during semiconductor fabrication with the aid of an optical alignment system, the semiconductor wafer having an alignment mark with regular structures, on the basis of which the position of the semiconductor wafer can be determined.

Abstract: A measurement mark (3) for determining the relative positional accuracy of a progressive projection onto a wafer (5), the projection being performed with two masks (3, 4), comprising two structure elements (10, 20) formed on a respective one of the masks (1, 2). The structure elements (10, 20) overlap with regard to their position on the masks so that, during the projection of the second structure element (20), an electrically conductive structure (30) formed on the basis of the first structure element on the wafer (5) is overformed by removal of a portion (31). In an electrical line width measurement, the reduced width (CD, CD30a) of the structure (30) is measured and compared either with the original width (62) or with that width (CD30b) of a further partial element (30b) produced by the overforming.

Abstract: A method for exposing a semiconductor wafer in an exposer includes applying a first resist layer on a layer covering an alignment mark. A microscope measuring instrument, which has a visible and an ultraviolet light source, uses the visible light source for aligning the wafer and uses the ultraviolet light source for exposing a region in the first resist layer above the alignment mark without using a mask to free expose the alignment marks. The semiconductor wafer is then developed, the alignment mark is etched free and covered again with a second resist, which is exposed in an exposer in order to transfer a mask structure following an alignment with the alignment mark. The capacity of expensive exposers is thus advantageously increased, and microscope measuring instruments can be used multifunctionally, for example for the free exposure and for the detection of defects.

Abstract: Exposure positions of exposure fields of semiconductor wafers are subsequently corrected individually in order to compensate for processes affecting the locational position of alignment marks and/or oblique measurement structures. Measurement structures are formed preferably in the frame region of product wafers comprising electrical circuits to be formed and their locational positions before and after the effect of the process that has an effect are compared individually for purpose of determining the positional displacement for each relevant exposure field. From this there is determined either directly a “shot”-fine correction value for the individual exposure or at least one nonlinear function for the correction in dependence on the position of the measurement structures on the wafer. The corrections are applied to the exposure fields after alignment to the alignment marks overformed by the process in dependence on their position on the wafer.

Abstract: An arrangement for transferring information/structures to wafers uses a stamp on which the information/structures to be transferred have been applied as elevated structures. The wafer is fixed on a chuck and is provided with a plastically deformable auxiliary patterning layer. In various implementations, the dimensions of the stamp approximately correspond to those of the wafer, the stamp is provided with the elevated structures essentially over the whole area, and/or the stamp and the wafer are in each case provided with mutually assigned pairs of alignment marks in such a way that the stamp can be positioned in a predetermined position on the wafer by means of an infrared positioning system and can be pressed into the plastically deformable auxiliary patterning layer.