Abstract: A lithography system configured to apply a pattern to a substrate, the system including a lithography apparatus configured to expose a layer of the substrate according to the pattern, and a machine learning controller configured to control the lithography system to optimize a property of the pattern, the machine learning controller configured to be trained on the basis of a property measured by a metrology unit configured to measure the property of the exposed pattern in the layer and/or a property associated with exposing the pattern onto the substrate, and to correct lithography system drift by adjusting one or more selected from: the lithography apparatus, a track unit configured to apply the layer on the substrate for lithographic exposure, and/or a control unit configured to control an automatic substrate flow among the track unit, the lithography apparatus, and the metrology unit.

Abstract: A lithography system configured to apply a pattern to a substrate, the system including a lithography apparatus configured to expose a layer of the substrate according to the pattern, and a machine learning controller configured to control the lithography system to optimize a property of the pattern, the machine learning controller configured to be trained on the basis of a property measured by a metrology unit configured to measure the property of the exposed pattern in the layer and/or a property associated with exposing the pattern onto the substrate, and to correct lithography system drift by adjusting one or more selected from: the lithography apparatus, a track unit configured to apply the layer on the substrate for lithographic exposure, and/or a control unit configured to control an automatic substrate flow among the track unit, the lithography apparatus, and the metrology unit.

Abstract: Methods and apparatus of manufacturing a semiconductor device are provided. Embodiments regard producing a first pattern in a first layer of a semiconductor substrate, producing a second pattern in a second layer of the semiconductor substrate, and matching the first pattern and the second pattern. The matching includes determining a mismatch between the first pattern and the second pattern that would occur without the matching and precorrecting the mismatch in the first layer.

Abstract: An arrangement for transferring information/structures to wafers uses a stamp on which the information/structures to be transferred have been applied as elevated structures. The wafer is fixed on a chuck and is provided with a plastically deformable auxiliary patterning layer. In various implementations, the dimensions of the stamp approximately correspond to those of the wafer, the stamp is provided with the elevated structures essentially over the whole area, and/or the stamp and the wafer are in each case provided with mutually assigned pairs of alignment marks in such a way that the stamp can be positioned in a predetermined position on the wafer by means of an infrared positioning system and can be pressed into the plastically deformable auxiliary patterning layer.

Abstract: A wafer exposure device includes a wafer stage. An optical exposure system exposes a wafer on the wafer stage. A sensor block measures a distance to a wafer provided on the wafer stage. The sensor block includes a plurality of height level sensors. Each height level sensor measures and outputs height level values. The wafer exposure device compares with one another the measured height level values outputted by respective height level sensors. The wafer exposure device calculates individual sensor position offset values to be attributed to the individual height level sensors. The wafer exposure device corrects the measured height level values output by the respective height level sensors using the calculated sensor position offset values of the respective height level sensor.

Abstract: An arrangement for transferring information/structures to wafers uses a stamp on which the information/structures to be transferred have been applied as elevated structures. The wafer is fixed on a chuck and is provided with a plastically deformable auxiliary patterning layer. In various implementations, the dimensions of the stamp approximately correspond to those of the wafer, the stamp is provided with the elevated structures essentially over the whole area, and/or the stamp and the wafer are in each case provided with mutually assigned pairs of alignment marks in such a way that the stamp can be positioned in a predetermined position on the wafer by means of an infrared positioning system and can be pressed into the plastically deformable auxiliary patterning layer.