Abstract: A method for aligning an electronic CMOS structure with respect to a buried structure in the case of a bonded and thinned back stack of semiconductor wafers. The method for aligning the electronic CMOS structure may include forming alignment marks in the process of fabricating the structure to be buried on a front side, which is used for bonding of the semiconductor wafer, which includes the structure to be buried. The alignment marks may be formed on the edge of the semiconductor wafer. The method for aligning the electronic CMOS structure may include providing a cover wafer with first thinned portions of the wafer thickness provided from the bonding side at positions corresponding to positions of the alignment marks.

Abstract: The invention is based on a method for aligning an electronic CMOS structure with respect to a buried structure in the case of a bonded and thinned back stack of semiconductor wafers. The method is intended to avoid “front side to rear side” alignments. The proposed method for aligning the electronic CMOS structure uses the formation of alignment marks (7; 7a, 7b) in the process of fabricating the structure to be buried on a front side, which is used for bonding of the semiconductor wafer (1), which includes the structure (2) to be buried. The alignment marks (7) are formed on the edge of the semiconductor wafer. A cover wafer (5) is provided with first thinned portions (10a; 10b) of the wafer thickness provided from the bonding side at positions corresponding to positions of the alignment marks (7). A plan view of the alignment marks (7) is obtained after wafer bonding.