Patents by Inventor Jen-Yu Lee

Jen-Yu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955154
    Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yi-Ting Wu, Yung-Ching Hsieh, Jian-Jhong Chen, Chia-Wei Lee
  • Patent number: 11956919
    Abstract: A cold plate is provided and includes: a housing disposed with a chamber; a base combined with the housing to form a working space separated from the chamber but connected with the chamber through an interconnecting structure to allow a working medium to flow within the chamber and the working space; a heat transfer structure disposed on the inner side of the base; and a pump disposed within the working space to drive the working medium in the working space. As such, the cold plate can provide better heat dissipation performance.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: April 9, 2024
    Assignee: AURAS TECHNOLOGY CO., LTD.
    Inventors: Chien-An Chen, Chien-Yu Chen, Tian-Li Ye, Jen-Hao Lin, Wei-Shen Lee
  • Patent number: 11948798
    Abstract: A method for manufacturing an integrated circuit includes patterning a plurality of photomask layers over a substrate, partially backfilling the patterned plurality of photomask layers with a first material using atomic layer deposition, completely backfilling the patterned plurality of photomask layers with a second material using atomic layer deposition, removing the plurality of photomask layers to form a masking structure comprising at least one of the first and second materials, and transferring a pattern formed by the masking structure to the substrate and removing the masking structure. The first material includes a silicon dioxide, silicon carbide, or carbon material, and the second material includes a metal oxide or metal nitride material.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yu Chang, Jung-Hau Shiu, Jen Hung Wang, Tze-Liang Lee
  • Publication number: 20240087207
    Abstract: Disclosed herein are system, method, and computer program product embodiments for reducing GPU load by programmatically controlling shading rates in computer graphics. GPU load may be reduced by applying different shading rates to different screen regions. By reading the depth buffer of previous frames and performing image processing, thresholds may be calculated that control the shading rates. The approach may be run on any platform that supports VRS hardware and primitive- or image-based VRS. The approach may be applied on a graphics driver installed on a client device, in a firmware layer between hardware and a driver, in a software layer between a driver and an application, or in hardware on the client device. The approach is flexible and adaptable and calculates and sets the variable rate shading based on the graphics generated by an application without requiring the application developer to manually set variable rate shading.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Applicant: MediaTek Inc.
    Inventors: Po-Yu HUANG, Shih-Chin LIN, Jen-Jung CHENG, Tu-Hsiu LEE
  • Patent number: 11930318
    Abstract: An electronic device, including a first substrate, a partition wall structure, a pressurizing component, a second substrate, a shell, and multiple first conductive parts, is provided. The first substrate has a through hole, and a first surface and a second surface that are opposite to each other. The partition wall structure is disposed on the first surface and surrounds to form a first chamber. The pressurizing component is disposed on the partition wall structure and covers the first chamber. The pressurizing component includes at least a mass and a vibration membrane. The shell is disposed on the second substrate and jointly forms a second chamber with the second substrate. The first chamber is formed in the second chamber. The multiple first conductive parts are disposed between the first substrate and the second substrate. There is a gap between any two adjacent first conductive parts.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: March 12, 2024
    Assignee: Merry Electronics Co., Ltd.
    Inventors: Yueh-Kang Lee, Jen-Yi Chen, Kai-Yu Jiang
  • Publication number: 20240076422
    Abstract: A supported metallocene catalyst includes a carrier and a metallocene component. The carrier includes an inorganic oxide particle and an alkyl aluminoxane material. The inorganic oxide particle includes at least one inorganic oxide compound selected from the group consisting of an oxide of Group 3A and an oxide of Group 4A. The alkyl aluminoxane material includes an alkyl aluminoxane compound and an alkyl aluminum compound that is present in amount ranging from greater than 0.01 wt % to less than 14 wt % base on 100 wt % of the alkyl aluminoxane material. The metallocene component is supported on the carrier, and includes one of a metallocene compound containing a metal from Group 3B, a metallocene compound containing a metal from Group 4B, and a combination thereof. A method for preparing the supported metallocene catalyst and a method for preparing polyolefin using the supported metallocene catalyst are also disclosed.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 7, 2024
    Inventors: Jing-Cherng TSAI, Jen-Long WU, Wen-Hao KANG, Kuei-Pin LIN, Jing-Yu LEE, Jun-Ye HONG, Zih-Yu SHIH, Cheng-Hung CHIANG, Gang-Wei SHEN, Yu-Chuan SUNG, Chung-Hua WENG, Hsing-Ya CHEN
  • Patent number: 9331107
    Abstract: A fabrication method of a pixel structure includes the following steps. A first metal layer is patterned to form a source electrode and a drain electrode. A semiconductor material layer is patterned to form a channel layer and a pixel pattern. A first insulation layer is formed to cover the channel layer, the source electrode, the drain electrode and the pixel pattern. A gate electrode is formed on the first insulation layer located above the channel layer. A second insulation layer is formed to cover the gate electrode and the first insulation layer. A pixel opening is formed in the first insulation layer and the second insulation layer to expose a partial region of the pixel pattern. The partial region of the pixel pattern exposed by the pixel opening is modified so as to form a pixel electrode electrically connected to the drain electrode.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: May 3, 2016
    Assignee: Au Optronics Corporation
    Inventors: Wei-Hao Tseng, Fan-Wei Chang, Shou-Wei Fang, Hong-Syu Chen, Jen-Yu Lee, Tsung-Hsiang Shih, Hung-Che Ting
  • Patent number: 9331106
    Abstract: A fabrication method of a pixel structure includes the following steps. A first metal layer is patterned to form a source electrode and a drain electrode. A semiconductor material layer is patterned to form a channel layer and a pixel pattern. A first insulation layer is formed to cover the channel layer, the source electrode, the drain electrode and the pixel pattern. A gate electrode is formed on the first insulation layer located above the channel layer. A second insulation layer is formed to cover the gate electrode and the first insulation layer. A pixel opening is formed in the first insulation layer and the second insulation layer to expose a partial region of the pixel pattern. The partial region of the pixel pattern exposed by the pixel opening is modified so as to form a pixel electrode electrically connected to the drain electrode.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: May 3, 2016
    Assignee: Au Optronics Corporation
    Inventors: Wei-Hao Tseng, Fan-Wei Chang, Shou-Wei Fang, Hong-Syu Chen, Jen-Yu Lee, Tsung-Hsiang Shih, Hung-Che Ting
  • Publication number: 20150270293
    Abstract: A fabrication method of a pixel structure includes the following steps. A first metal layer is patterned to form a source electrode and a drain electrode. A semiconductor material layer is patterned to form a channel layer and a pixel pattern. A first insulation layer is formed to cover the channel layer, the source electrode, the drain electrode and the pixel pattern. A gate electrode is formed on the first insulation layer located above the channel layer. A second insulation layer is formed to cover the gate electrode and the first insulation layer. A pixel opening is formed in the first insulation layer and the second insulation layer to expose a partial region of the pixel pattern. The partial region of the pixel pattern exposed by the pixel opening is modified so as to form a pixel electrode electrically connected to the drain electrode.
    Type: Application
    Filed: May 22, 2015
    Publication date: September 24, 2015
    Inventors: Wei-Hao Tseng, Fan-Wei Chang, Shou-Wei Fang, Hong-Syu Chen, Jen-Yu Lee, Tsung-Hsiang Shih, Hung-Che Ting
  • Publication number: 20150123111
    Abstract: A fabrication method of a pixel structure includes the following steps. A first metal layer is patterned to form a source electrode and a drain electrode. A semiconductor material layer is patterned to form a channel layer and a pixel pattern. A first insulation layer is formed to cover the channel layer, the source electrode, the drain electrode and the pixel pattern. A gate electrode is formed on the first insulation layer located above the channel layer. A second insulation layer is formed to cover the gate electrode and the first insulation layer. A pixel opening is formed in the first insulation layer and the second insulation layer to expose a partial region of the pixel pattern. The partial region of the pixel pattern exposed by the pixel opening is modified so as to form a pixel electrode electrically connected to the drain electrode.
    Type: Application
    Filed: March 20, 2014
    Publication date: May 7, 2015
    Applicant: Au Optronics Corporation
    Inventors: Wei-Hao Tseng, Fan-Wei Chang, Shou-Wei Fang, Hong-Syu Chen, Jen-Yu Lee, Tsung-Hsiang Shih, Hung-Che Ting
  • Patent number: 8541779
    Abstract: A pixel structure of an organic electroluminescence apparatus includes at least an active device connected to a scan line and a data line, a first electrode, a dielectric material layer, a first isolating layer, a second isolating layer, an organic light-emitting material layer and a second electrode. The dielectric material layer is disposed on the first electrode and has a first opening to expose the first electrode. The first isolating layer disposed on the dielectric material layer includes an oxide semiconductor material and has a second opening to expose the first electrode. The second isolating layer is disposed on the first isolating layer and has a third opening to expose the first electrode in the first opening and the first isolating layer in a sidewall of the second opening. The organic light-emitting material layer is in the third opening. The second electrode is on the organic light-emitting layer.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: September 24, 2013
    Assignee: Au Optronics Corporation
    Inventors: Hong-Syu Chen, Shou-Wei Fang, Jen-Yu Lee, Tsung-Hsiang Shih, Hsueh-Hsing Lu, Chia-Yu Chen
  • Publication number: 20090244822
    Abstract: A touch control pen for a portable electronic device includes a resilient positioning sleeve sleeved sealingly on an elongate main body and disposed adjacent to a head end of the main body. When the touch control pen is inserted into a slot defined by a looped surrounding wall of a housing of the portable electronic device, the positioning sleeve contacts watertightly an inner annular surface of the looped surrounding wall of the housing.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Inventors: Li-Ying Chen, En-Guang Huang, Jen-Yu Lee, Fei-Ming Su
  • Publication number: 20070071438
    Abstract: A handheld electronic device includes a casing, a camera unit, and a sealing unit. The casing confines an accommodating space, and is formed with a recess that is defined by a recess-defining wall. The recess-defining wall is formed with a hole that is in spatial communication with the recess and the accommodating space. The camera unit includes a camera housing and an electrical wire. The camera housing is disposed in the recess, and has a first end portion that is received rotatably in the hole in the recess-defining wall. The electrical wire has a first end portion that extends into the camera housing, and a second end portion that extends into the accommodating space. The sealing unit is disposed between and is in airtight contact with the recess-defining wall and the camera housing.
    Type: Application
    Filed: September 27, 2005
    Publication date: March 29, 2007
    Applicant: Universal Scientific Industrial Co., Ltd.
    Inventors: Baron Huang, Jen-Yu Lee, Fei-Mi Su, Shun-Fu Chen
  • Patent number: 6997743
    Abstract: A card-securing device has a plate body for securing a card to a printed circuit board. The plate body includes a main plate, and a pair of side-securing plates and an end-securing plate which extend transversely from the main plate. Each of the side-securing plates and the end-securing plate has a base portion connected to the main plate, a neck portion extending and reduced in length from the corresponding base portion, and a tab portion bent and extending from the corresponding neck portion through the printed circuit board to anchor on a bottom surface of the printed circuit board.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: February 14, 2006
    Assignee: Universal Scientific Industrial Co., Ltd.
    Inventors: Fei-Ming Su, Eng-Guang Huang, Jen-Yu Lee