Abstract: Integrated circuit memory devices include an array of memory cells and a row address generator circuit which generates first and second different sequences of addresses during first and second refresh modes, respectively, and also repeats at least one of the addresses in the first sequence as an address in the second sequence when transitioning from the first refresh mode to the second refresh mode. The generator circuit may also perform the function of generating row addresses during the first and second refresh modes with the most significant bit of a row address being toggled with each consecutive row address during the first refresh mode. The first refresh mode may be a CAS-before-RAS refresh mode, the second refresh mode may be a self-refresh mode and the address in at least one of the first and second periods of the self-refresh mode may be equivalent to an address in the last period of a preceding CAS-before-RAS refresh mode when transitioning from the first refresh mode to the second refresh mode.

Abstract: A semiconductor memory device comprises a plurality of normal memory cell arrays having a first and a second data state, a plurality of redundant memory cell arrays having a first and a second data state for substituting for the normal memory cell arrays, a plurality of input/output lines, a plurality of complementary input/output lines, a plurality of first control signals for substituting a redundant memory cell array having the first data state for a defective normal memory cell array having the first data state, and a plurality of second control signals for substituting a redundant memory cell array having the second data state for a defective normal memory cell array having the second data state. In the device, a control circuit for transmitting the complementary input/output data to the plurality of input/output lines, and the input/output data to the plurality of complementary input/output data lines according to the circumstances is provided.