Patents by Inventor Jeon-Taek Im
Jeon-Taek Im has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9159438Abstract: A NAND flash memory in which a command/address pin is separated from a data input/output pin. The NAND flash memory includes a memory cell array used for storing data, a command/address pin through which a command and an address are received for transmitting data in the memory cell array, and a data input/output pin through which data are transmitted in the memory cell array. The command/address pin is separated from the data input/output pin in the NAND flash memory. Data input/output speed is increased. Furthermore, the NAND flash memory can perform a bank interleaving operation with a minimal delay time.Type: GrantFiled: June 25, 2013Date of Patent: October 13, 2015Assignee: Samsung Electronics, Co., Ltd.Inventor: Jeon-Taek Im
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Publication number: 20130286737Abstract: A NAND flash memory in which a command/address pin is separated from a data input/output pin. The NAND flash memory includes a memory cell array used for storing data, a command/address pin through which a command and an address are received for transmitting data in the memory cell array, and a data input/output pin through which data are transmitted in the memory cell array. The command/address pin is separated from the data input/output pin in the NAND flash memory. Data input/output speed is increased. Furthermore, the NAND flash memory can perform a bank interleaving operation with a minimal delay time.Type: ApplicationFiled: June 25, 2013Publication date: October 31, 2013Inventor: JEON-TAEK IM
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Patent number: 8312206Abstract: A memory module and a memory module system are provided. The memory module system includes a plurality of memory modules each module comprising a plurality of memory blocks and a plurality of corresponding routers each storing a channel identification (ID) and a module ID corresponding to one or more memory blocks; and a controller configured to access the memory modules. During initialization, the controller reads and stores the channel ID and the module ID from each of the routers. The controller outputs a channel ID and a module ID that correspond to one or more memory blocks to be accessed.Type: GrantFiled: March 29, 2011Date of Patent: November 13, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Jeon Taek Im
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Patent number: 8240575Abstract: A multi-interface card includes smart card interface, memory card interface, card controller and memory module. The smart card interface interfaces with a smart card host using a smart card protocol. The memory card interface interfaces with a memory card host using a memory card protocol. The card controller controls the smart card host and memory card host so that the smart card host and the memory card host simultaneously interface with the smart card and the memory card interfaces, respectively. The memory module stores data transferred from the smart card host and memory card host. The multi-interface card simultaneously supports the smart card interface and the memory card interface. Thus, the one multi-interface card can support a subscriber authentication function and a data storage function.Type: GrantFiled: April 15, 2009Date of Patent: August 14, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Kyoung-Hun Kim, Seong-Hyun Kim, Jong-Hoon Shin, Yong-Joo Park, Zang-Hee Cho, Jong-Sang Choi, Jeon-Taek Im
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Patent number: 8209527Abstract: A booting method of a digital processing having a first processor and a second processor is provided. An interface between the first processor and the outside is stopped. A second processor program code is transmitted to a second memory from a first memory. A second stage loader (SSL) for the first processor is transmitted to a buffer of the second processor from the first memory. A first processor program code is transmitted to the second memory from the first memory under the control of the second processor and an interface between the first processor and the outside is resumed. The first processor program code is downloaded fast into the second memory to decrease booting time of the digital processing system.Type: GrantFiled: April 27, 2009Date of Patent: June 26, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jeon-Taek Im, Young-Min Lee, Han-Gu Sohn, Jin-Hyoung Kwon, Sung-Jae Byun, Yun-Tae Lee, Gyoo-Cheol Hwang
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Publication number: 20110317531Abstract: An optical disk drive includes a non-volatile memory. The optical disk drive is booted based on driving information stored in the non-volatile memory. When a write command is received from a host, the optical disk drive stores data to be recorded in an optical medium in the non-volatile memory and then writes the data in the optical medium independent of the host.Type: ApplicationFiled: September 1, 2011Publication date: December 29, 2011Inventors: Sung-Kook Bang, Jeon-Taek Im
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Patent number: 8019934Abstract: An optical disk drive includes a non-volatile memory. The optical disk drive is booted based on driving information stored in the non-volatile memory. When a write command is received from a host, the optical disk drive stores data to be recorded in an optical medium in the non-volatile memory and then writes the data in the optical medium independent of the host.Type: GrantFiled: June 18, 2007Date of Patent: September 13, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Kook Bang, Jeon-Taek Im
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Publication number: 20110179213Abstract: A memory module and a memory module system are provided. The memory module system includes a plurality of memory modules each module comprising a plurality of memory blocks and a plurality of corresponding routers each storing a channel identification (ID) and a module ID corresponding to one or more memory blocks; and a controller configured to access the memory modules. During initialization, the controller reads and stores the channel ID and the module ID from each of the routers. The controller outputs a channel ID and a module ID that correspond to one or more memory blocks to be accessed.Type: ApplicationFiled: March 29, 2011Publication date: July 21, 2011Inventor: Jeon Taek IM
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Patent number: 7921256Abstract: A memory module and a memory module system are provided. The memory module system includes a plurality of memory modules each module comprising a plurality of memory blocks and a plurality of corresponding routers each storing a channel identification (ID) and a module ID corresponding to one or more memory blocks; and a controller configured to access the memory modules. During initialization, the controller reads and stores the channel ID and the module ID from each of the routers. The controller outputs a channel ID and a module ID that correspond to one or more memory blocks to be accessed.Type: GrantFiled: February 6, 2008Date of Patent: April 5, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Jeon Taek Im
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Patent number: 7873753Abstract: A controller and a memory subsystem including a plurality of memory banks each having a plurality of memory devices, in which the controller includes a memory device configured to store an identification (ID) of each of the plurality of memory banks; and a control logic configured to read an ID of a memory bank to be accessed among the plurality of memory banks from the memory device, then output the ID, and then output a command. Each of the plurality of memory devices includes an input port, a register configured to store an ID of each memory device, and a determination circuit configured to receive and compare an ID input via the input port with the ID stored in the register and to generate a control signal according to a result of the comparison. The input port is enabled or disabled in response to the control signal.Type: GrantFiled: August 24, 2007Date of Patent: January 18, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Jeon Taek Im
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Patent number: 7733680Abstract: A non-volatile memory module for preventing system failure and a system including the same, in which the non-volatile memory system includes a first socket and a second socket each having a notch coupler, a first memory module, a memory controller configured to control the first memory module, and a printed circuit board on which the memory controller and the first and second sockets are installed and electrical signal lines are formed between the memory controller and the first and second sockets. The first memory includes a plurality of non-volatile memory devices and stores system software. The first memory module has a structure such that it can be installed at the first socket but cannot be installed at the second socket. The non-volatile memory system may further include a second memory module for an extension of the memory capacity. The second memory module has a structure such that it can be installed at the second socket but cannot be installed at the first socket.Type: GrantFiled: December 21, 2007Date of Patent: June 8, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Jeon-Taek Im
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Patent number: 7610061Abstract: A communication device and method is provided, comprising: a signal modulator/demodulator having a digital signal processor for effecting radio communications; and an application processor (AP) having a central processing unit and a master controller for controlling via a common bus a plurality of peripherals including an interface with the signal modulator/demodulator, wherein a memory shared by the modem and the AP is controlled via the interface. The plurality of peripherals include at least one of an image capture module, a display, and a flash memory. The master controller controls the plurality of peripherals by issuing a packetized command commonly receivable by the plurality of peripherals over the common bus, the packetized command includes a module device select signal used for selecting one of the peripherals.Type: GrantFiled: March 30, 2004Date of Patent: October 27, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Woon-Sik Suh, Jeon Taek Im, Jin-Aeon Lee
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Patent number: 7596353Abstract: The present invention provides a system with a plurality of Bluetooth dongles connected to a single host. Each dongle is connected to a different port on the host and each dongle can accommodate a piconet of up to seven Bluetooth devices. The host communicates with the Bluetooth devices via Bluetooth channels. The host includes an application layer, a Host Control Interface (HCI) layer and an interface device driver layer. An Interface Map Table (IMT) is stored in the host. The IMT associates each port on the host with the BD address of a particular Bluetooth dongle and with the channels associated with the particular dongle. The HCI layer and the Interface handler layer consult the IMT to direct commands and data to the correct port on the host.Type: GrantFiled: March 21, 2005Date of Patent: September 29, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Suk Chung, Sung-Bong Kang, Jeon-Taek Im, Joong-Kyu Choi
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Publication number: 20090210691Abstract: A booting method of a digital processing having a first processor and a second processor is provided. An interface between the first processor and the outside is stopped. A second processor program code is transmitted to a second memory from a first memory. A second stage loader (SSL) for the first processor is transmitted to a buffer of the second processor from the first memory. A first processor program code is transmitted to the second memory from the first memory under the control of the second processor and an interface between the first processor and the outside is resumed. The first processor program code is downloaded fast into the second memory to decrease booting time of the digital processing system.Type: ApplicationFiled: April 27, 2009Publication date: August 20, 2009Inventors: Jeon-Taek Im, Young-Min Lee, Han-Gu Sohn, Jin-Hyoung Kwon, Sung-Jae Byun, Yun-Tae Lee, Gyoo-Cheol Hwang
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Publication number: 20090200368Abstract: A multi-interface card includes smart card interface, memory card interface, card controller and memory module. The smart card interface interfaces with a smart card host using a smart card protocol. The memory card interface interfaces with a memory card host using a memory card protocol. The card controller controls the smart card host and memory card host so that the smart card host and the memory card host simultaneously interface with the smart card and the memory card interfaces, respectively. The memory module stores data transferred from the smart card host and memory card host. The multi-interface card simultaneously supports the smart card interface and the memory card interface. Thus, the one multi-interface card can support a subscriber authentication function and a data storage function.Type: ApplicationFiled: April 15, 2009Publication date: August 13, 2009Inventors: Kyoung-Hun Kim, Seong-Hyun Kim, Jong-Hoon Shin, Yong-Joo Park, Zang-Hee Cho, Jong-sang Choi, Jeon-Taek Im
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Patent number: 7520438Abstract: A multi-interface card includes smart card interface, memory card interface, card controller and memory module. The smart card interface interfaces with a smart card host using a smart card protocol. The memory card interface interfaces with a memory card host using a memory card protocol. The card controller controls the smart card host and memory card host so that the smart card host and the memory card host simultaneously interface with the smart card and the memory card interfaces, respectively. The memory module stores data transferred from the smart card host and memory card host. The multi-interface card simultaneously supports the smart card interface and the memory card interface. Thus, the one multi-interface card can support a subscriber authentication function and a data storage function.Type: GrantFiled: August 26, 2005Date of Patent: April 21, 2009Assignee: Samsung Electronics, Co., Ltd.Inventors: Kyoung-Hun Kim, Seong-Hyun Kim, Jong-Hoon Shin, Yong-Joo Park, Zang-Hee Cho, Jong-Sang Choi, Jeon-Taek Im
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Publication number: 20080222378Abstract: A memory module and a memory module system are provided. The memory module system includes a plurality of memory modules each module comprising a plurality of memory blocks and a plurality of corresponding routers each storing a channel identification (ID) and a module ID corresponding to one or more memory blocks; and a controller configured to access the memory modules. During initialization, the controller reads and stores the channel ID and the module ID from each of the routers. The controller outputs a channel ID and a module ID that correspond to one or more memory blocks to be accessed.Type: ApplicationFiled: February 6, 2008Publication date: September 11, 2008Inventor: Jeon Taek IM
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Publication number: 20080209077Abstract: A controller and a memory subsystem including a plurality of memory banks each having a plurality of memory devices, in which the controller includes a memory device configured to store an identification (ID) of each of the plurality of memory banks; and a control logic configured to read an ID of a memory bank to be accessed among the plurality of memory banks from the memory device, then output the ID, and then output a command. Each of the plurality of memory devices includes an input port, a register configured to store an ID of each memory device, and a determination circuit configured to receive and compare an ID input via the input port with the ID stored in the register and to generate a control signal according to a result of the comparison. The input port is enabled or disabled in response to the control signal.Type: ApplicationFiled: August 24, 2007Publication date: August 28, 2008Inventor: JEON TAEK IM
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Publication number: 20080172500Abstract: A memory system and method of operation are disclosed. The system includes a memory device having multiple RAMs, and a memory controller having a plurality of controllers, each one of the plurality of controllers is configured to generate an address signal and a control signal controlling read/write operations in a corresponding one of the RAMs. The memory controller includes a single common control signal output port communicating control signals generated by the controllers, and a single common address signal output port communicating address signals generated by the controllers.Type: ApplicationFiled: January 9, 2008Publication date: July 17, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Jeon-Taek IM
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Publication number: 20080158956Abstract: A non-volatile memory module for preventing system failure and a system including the same, in which the non-volatile memory system includes a first socket and a second socket each having a notch coupler, a first memory module, a memory controller configured to control the first memory module, and a printed circuit board on which the memory controller and the first and second sockets are installed and electrical signal lines are formed between the memory controller and the first and second sockets. The first memory includes a plurality of non-volatile memory devices and stores system software. The first memory module has a structure such that it can be installed at the first socket but cannot be installed at the second socket. The non-volatile memory system may further include a second memory module for an extension of the memory capacity. The second memory module has a structure such that it can be installed at the second socket but cannot be installed at the first socket.Type: ApplicationFiled: December 21, 2007Publication date: July 3, 2008Inventor: Jeon-Taek Im