Abstract: The present invention relates to an inverter for high voltage full swing output, for generating an inverter output changing into full swing corresponding to a supply voltage of a high voltage circuit which is m (integer) times higher than a supply voltage of a low voltage circuit, the inverter including a switching circuit having 2 m transistors stacked one upon another, a feedback control circuit supplying gates of the 2 m transistors of the switching circuit with a bias voltage by reducing a full swing inverter output voltage, and a shield voltage source generating a shield voltage to control transmission of the bias voltage.

Abstract: A parallel multiplier includes m multiplexers and a plurality of adders. The multiplexers receive an n-bit multiplicand and n-bit zero (0) through two input terminals, respectively, and one (1) bit of a m-bit multiplier through a select terminal to selectively output the n-bit multiplicand when the one bit of the m-bit multiplier is “1 ” and the n-bit zero (0) when the one bit of the m-bit multiplier is “0”. The adders receive two of the n-bit output data from the multiplexers to output an n+2 bit partial product or an n+m bit product by adding two neighboring output data from the multiplexers after 1 bit downshifting the (less significant) neighboring output data corresponding to the less significant bit of the m-bit multiplier. A final adder can output an n+m bit product by adding two (n+x bit) partial products after downshifting a selected one.