Abstract: A storage device comprises a nonvolatile memory configured to store data that is written in size units of a mapping size, and a storage controller configured to transmit a command to the nonvolatile memory. The storage controller includes a host interface configured to receive a write command from a host device, the write command including a command to write first data to a first address, the first data having a first size smaller than the mapping size. The storage controller includes processing circuitry configured to transmit a read command to the nonvolatile memory, to cause the nonvolatile memory to read second data stored in the nonvolatile memory addressed based on the first address, in response to a determination that the first size is smaller than the mapping size and before the first data is received at the storage controller through the host interface.

Abstract: A storage device comprises a nonvolatile memory configured to store data that is written in size units of a mapping size, and a storage controller configured to transmit a command to the nonvolatile memory. The storage controller includes a host interface configured to receive a write command from a host device, the write command including a command to write first data to a first address, the first data having a first size smaller than the mapping size. The storage controller includes processing circuitry configured to transmit a read command to the nonvolatile memory, to cause the nonvolatile memory to read second data stored in the nonvolatile memory addressed based on the first address, in response to a determination that the first size is smaller than the mapping size and before the first data is received at the storage controller through the host interface.

Abstract: Described is a memory controller interfacing with a host and a nonvolatile memory. The memory controller may include a buffer unit configured to store an input address table and a first hot address table; and a processing unit configured to judge whether an address from the host coincides with one of addresses stored in the input address table and to store the address from the host in the first hot address table according to the judgment.

Abstract: An operating method of a memory controller includes classifying a plurality of blocks in a memory cell array included in a flash memory into a first group and a second group according to the number of error bits in data programmed to each of the blocks, and creating a combinational block by combining a first block from the first group with a second block from the second group.

Abstract: A data processing device for a storage device can include a dictionary storage unit that is configured to store a plurality of dictionaries and a compression unit that is configured to determine a selected dictionary from the plurality of dictionaries based on received data, and compress the received data using the selected dictionary to provide compressed data. Each of the plurality of dictionaries can include a plurality of pattern-symbol correspondence relations defining a one-to-one correspondence between respective ones of a plurality of patterns and respective ones of a plurality of symbols.

Abstract: A method is provided for operating a data storage device comprising a storage medium and a controller configured to control operations of the storage medium. The method comprises determining whether a read-requested data strip is an error data strip, reading a plurality of data strips in a stripe comprising the read-requested data strip when the read-requested data strip is the error data strip, outputting a data strip recovered using the other data strip except the error data strip among the plurality of data strips, and writing the recovered data strip and the other data strips into the storage medium.

Abstract: According to an aspect of the inventive concepts, there is provided a non-volatile memory device including a memory array with at least one stripe. The at least one stripe includes at least one parity page and at least one data page. The non-volatile memory device further includes a chip controller. The chip controller includes an operation module configured to perform an operation on data input from the outside of the memory device, to store a result of the performing, and to program the result of the performing into the at least one parity page. The chip controller further includes a data buffer configured to store the input data and to program the input data into the at least one data page.

Abstract: A data processing device for a storage device can include a dictionary storage unit that is configured to store a plurality of dictionaries and a compression unit that is configured to determine a selected dictionary from the plurality of dictionaries based on received data, and compress the received data using the selected dictionary to provide compressed data. Each of the plurality of dictionaries can include a plurality of pattern-symbol correspondence relations defining a one-to-one correspondence between respective ones of a plurality of patterns and respective ones of a plurality of symbols.

Abstract: A method is provided for operating a data storage device comprising a storage medium and a controller configured to control operations of the storage medium. The method comprises determining whether a read-requested data strip is an error data strip, reading a plurality of data strips in a stripe comprising the read-requested data strip when the read-requested data strip is the error data strip, outputting a data strip recovered using the other data strip except the error data strip among the plurality of data strips, and writing the recovered data strip and the other data strips into the storage medium.

Abstract: An operating method of a memory controller includes classifying a plurality of blocks in a memory cell array included in a flash memory into a first group and a second group according to the number of error bits in data programmed to each of the blocks, and creating a combinational block by combining a first block from the first group with a second block from the second group.

Abstract: Described is a memory controller interfacing with a host and a nonvolatile memory. The memory controller may include a buffer unit configured to store an input address table and a first hot address table; and a processing unit configured to judge whether an address from the host coincides with one of addresses stored in the input address table and to store the address from the host in the first hot address table according to the judgment.