Patents by Inventor Jeong-Don Lim

Jeong-Don Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8254184
    Abstract: A semiconductor memory device includes a latency controller which provides a power-saving effect. The latency controller includes a first-in first-out (FIFO) register. After a read command is applied, when a precharge command or power-down command is applied, the latency controller outputs a latency signal corresponding to the applied read command and blocks application of sampling and transmission clock signals to the FIFO register.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: August 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Soo Sohn, Jeong-Don Lim, Kwang-Il Park
  • Patent number: 8189403
    Abstract: A high speed linear differential amplifier (HSLDA) having automatic gain adjustment to maximize linearity regardless of manufacturing process, changes in temperature, or swing width change of the input signal. The HSLDA comprises a differential amplifier, and a control signal generator including a replica differential amplifier, a reference voltage generator, and a comparator. The comparator outputs a control signal that automatically adjusts the gain of the high speed linear differential amplifier and of the replica differential amplifier. The replica differential amplifier receives predetermined complementary voltages as input signals and outputs a replica output signal to the comparator. The reference voltage generator outputs a voltage to the comparator at which linearity of the output signal of the differential amplifier is maximized. The control signal equalizes the voltage level of the replica output signal and the reference voltage, and controls the gain of the differential amplifier.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: May 29, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Soo Sohn, Jeong-Don Lim, Kwang-Il Park
  • Patent number: 8169268
    Abstract: An oscillation circuit, and a semiconductor device incorporating same, include: an oscillation unit with a plurality of inverters and configured to perform signal transmission between first and second nodes of the inverters such that each of the inverters performs an oscillation operation to generate clock signals having different phases when a control signal is activated, and latch a clock signal of the second node and cut off the signal transmission between the first and second nodes to stop the oscillation operations of the inverters when the control signal is deactivated; and a control unit to activate the control signal when an oscillation enable signal is activated, and deactivate the control signal using one of a clock signal output from an inverter connected to the second node and clock signals of which the phases lag that of a clock signal of the first node, when the oscillation enable signal is deactivated.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: May 1, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Hoon Lim, Jeong-Don Lim, Kwang-Il Park
  • Publication number: 20110001569
    Abstract: An oscillation circuit and a semiconductor device incorporating same are provided. The oscillation circuit includes an oscillation unit including a plurality of inverters and configured to perform signal transmission between first and second nodes of the inverters such that each of the inverters performs an oscillation operation to generate clock signals having different phases, when a control signal is activated, and latch a clock signal of the second node and cut off the signal transmission between the first and second nodes to stop the oscillation operations of the inverters, when the control signal is deactivated, and a control unit configured to activate the control signal when an oscillation enable signal is activated, and deactivate the control signal using one of a clock signal output from an inverter connected to the second node among the plurality of inverters and clock signals of which the phases lead that of a clock signal of the first node, when the oscillation enable signal is deactivated.
    Type: Application
    Filed: May 17, 2010
    Publication date: January 6, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Hoon LIM, Jeong-Don LIM, Kwang-Il PARK
  • Publication number: 20110001562
    Abstract: A high speed linear differential amplifier (HSLDA) having automatic gain adjustment to maximize linearity regardless of manufacturing process, changes in temperature, or swing width change of the input signal. The HSLDA comprises a differential amplifier, and a control signal generator including a replica differential amplifier, a reference voltage generator, and a comparator. The comparator outputs a control signal that automatically adjusts the gain of the high speed linear differential amplifier and of the replica differential amplifier. The replica differential amplifier receives predetermined complementary voltages as input signals and outputs a replica output signal to the comparator. The reference voltage generator outputs a voltage to the comparator at which linearity of the output signal of the differential amplifier is maximized. The control signal equalizes the voltage level of the replica output signal and the reference voltage, and controls the gain of the differential amplifier.
    Type: Application
    Filed: June 17, 2010
    Publication date: January 6, 2011
    Inventors: Young-Soo Sohn, Jeong-Don Lim, Kwang-Il Park
  • Publication number: 20100329049
    Abstract: A semiconductor memory device includes a latency controller which provides a power-saving effect. The latency controller includes a first-in first-out (FIFO) register. After a read command is applied, when a precharge command or power-down command is applied, the latency controller outputs a latency signal corresponding to the applied read command and blocks application of sampling and transmission clock signals to the FIFO register.
    Type: Application
    Filed: June 22, 2010
    Publication date: December 30, 2010
    Inventors: YOUNG-SOO SOHN, Jeong-Don Lim, Kwang-Il Park
  • Patent number: 7853840
    Abstract: A semiconductor memory device and methods thereof are provided. The example semiconductor memory device may include an internal address generating circuit operating in accordance with a first addressing protocol during normal operation and operating in accordance with a second addressing protocol during a test operation, the first addressing protocol associated with a first number of clock cycles for transferring a memory address and the second addressing protocol associated with a second number of clock cycles for transferring a memory address, the first number of clock cycles being greater than the second number of clock cycles.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: December 14, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Sang Park, Jeong-Don Lim, Youn-Sik Park
  • Publication number: 20100148819
    Abstract: A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.
    Type: Application
    Filed: February 4, 2010
    Publication date: June 17, 2010
    Inventors: Seung-Jun Bae, Jeong-Don Lim, Gil-Shin Moon, Kwang-II Park
  • Publication number: 20100091600
    Abstract: Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.
    Type: Application
    Filed: December 11, 2009
    Publication date: April 15, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Jin Kim, Seong-Jin Jang, Jeong-Don Lim, Kwang-Il Park, Ho-Young Song, Woo-Jin Lee
  • Patent number: 7688102
    Abstract: A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: March 30, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jun Bae, Jeong-Don Lim, Gil-Shin Moon, Kwang-Il Park
  • Patent number: 7656742
    Abstract: Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: February 2, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Jin Kim, Seong-Jin Jang, Jeong-Don Lim, Kwang-Il Park, Ho-Young Song, Woo-Jin Lee
  • Patent number: 7643355
    Abstract: According to an example embodiment, a semiconductor memory device may include a memory core, input circuit, and/or an output circuit. The input circuit may be configured to generate second data from first data using latch circuits operating in response to input control signals enabled during different periods. The input circuit may be further configured to provide the second data to the memory core. The second data may have 2N times the number of bits of the first data, where N is a positive integer. The output circuit may be configured to generate fourth data from third data using latch circuits operating in response to output control signals enabled during different periods. The output circuit may be further configured to provide the fourth data to data output pins. The fourth data may have ½N times the number of bits of the third data. A method of inputting/outputting data is also provided.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: January 5, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joung-Yeal Kim, Jeong-Don Lim, Sung-Hoon Kim, Woo-Jin Lee
  • Publication number: 20080225626
    Abstract: Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.
    Type: Application
    Filed: May 28, 2008
    Publication date: September 18, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Jin KIM, Seong-Jin JANG, Jeong-Don LIM, Kwang-Il PARK, Ho-Young SONG, Woo-Jin LEE
  • Patent number: 7400541
    Abstract: A data bus inversion (DBI) circuit includes at least one DBI block configured to invert an input data signal based on the logic state of input data bits. The DBI block includes a comparison deciding unit configured to generate, in a first mode, a comparison signal based on the number of changed bits by comparing respective bit signals of the input data signal and a previous input data signal. The comparison deciding unit generates an inversion control signal which controls whether the input data will be inverted or not. In a second mode, the comparison deciding unit generates an inversion control signal based on the predominant logic state of the input data signal bits. A data converting unit is configured to invert the input data signal in response to the inversion control signal. Method embodiments are also disclosed.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: July 15, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-Jin Jang, Jeong-Don Lim
  • Patent number: 7394720
    Abstract: Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: July 1, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Jin Kim, Seong-Jin Jang, Jeong-Don Lim, Kwang-Il Park, Ho-Young Song, Woo-Jin Lee
  • Publication number: 20080094932
    Abstract: A semiconductor memory device and methods thereof are provided. The example semiconductor memory device may include an internal address generating circuit operating in accordance with a first addressing protocol during normal operation and operating in accordance with a second addressing protocol during a test operation, the first addressing protocol associated with a first number of clock cycles for transferring a memory address and the second addressing protocol associated with a second number of clock cycles for transferring a memory address, the first number of clock cycles being greater than the second number of clock cycles.
    Type: Application
    Filed: February 6, 2007
    Publication date: April 24, 2008
    Inventors: Min-Sang Park, Jeong-Don Lim, Youn-Sik Park
  • Publication number: 20080056018
    Abstract: According to an example embodiment, a semiconductor memory device may include a memory core, input circuit, and/or an output circuit. The input circuit may be configured to generate second data from first data using latch circuits operating in response to input control signals enabled during different periods. The input circuit may be further configured to provide the second data to the memory core. The second data may have 2N times the number of bits of the first data, where N is a positive integer. The output circuit may be configured to generate fourth data from third data using latch circuits operating in response to output control signals enabled during different periods. The output circuit may be further configured to provide the fourth data to data output pins. The fourth data may have ½N times the number of bits of the third data. A method of inputting/outputting data is also provided.
    Type: Application
    Filed: September 5, 2007
    Publication date: March 6, 2008
    Inventors: Joung-Yeal Kim, Jeong-Don Lim, Sung-Hoon Kim, Woo-Jin Lee
  • Publication number: 20080019451
    Abstract: A data bus inversion (DBI) circuit includes at least one DBI block configured to invert an input data signal based on the logic state of input data bits. The DBI block includes a comparison deciding unit configured to generate, in a first mode, a comparison signal based on the number of changed bits by comparing respective bit signals of the input data signal and a previous input data signal. The comparison deciding unit generates an inversion control signal which controls whether the input data will be inverted or not. In a second mode, the comparison deciding unit generates an inversion control signal based on the predominant logic state of the input data signal bits. A data converting unit is configured to invert the input data signal in response to the inversion control signal. Method embodiments are also disclosed.
    Type: Application
    Filed: September 28, 2007
    Publication date: January 24, 2008
    Inventors: Seong-Jin Jang, Jeong-Don Lim
  • Publication number: 20080001626
    Abstract: A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 3, 2008
    Inventors: Seung-Jun Bae, Jeong-Don Lim, Gil-Shin Moon, Kwang-Il Park
  • Patent number: 7280412
    Abstract: A data bus inversion (DBI) circuit includes at least one DBI block configured to invert an input data signal based on the logic state of input data bits. The DBI block includes a comparison deciding unit configured to generate, in a first mode, a comparison signal based on the number of changed bits by comparing respective bit signals of the input data signal and a previous input data signal. The comparison deciding unit generates an inversion control signal which controls whether the input data will be inverted or not. In a second mode, the comparison deciding unit generates an inversion control signal based on the predominant logic state of the input data signal bits. A data converting unit is configured to invert the input data signal in response to the inversion control signal. Method embodiments are also disclosed.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: October 9, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-Jin Jang, Jeong-Don Lim