Abstract: According to an exemplary embodiment of the present disclosure, disclosed is an aluminum coated blank that includes a first coated steel sheet; a second coated steel sheet connected to the first coated steel sheet; and a joint portion that connects the first coated steel sheet to the second coated steel plate at a boundary between the first coated steel sheet and the second coated steel sheet.

Abstract: According to an exemplary embodiment of the present disclosure, disclosed is an aluminum coated blank that includes a first coated steel sheet; a second coated steel sheet connected to the first coated steel sheet; and a joint portion that connects the first coated steel sheet to the second coated steel plate at a boundary between the first coated steel sheet and the second coated steel sheet.

Abstract: An olefin-based polymer, a film prepared from the olefin-based polymer, and preparation methods for manufacturing the olefin-based polymer and the film are disclosed. The olefin-based polymer has excellent processability, and a film prepared from the olefin-based polymer, particularly, a linear low density polyethylene film has excellent mechanical strength, in particular, drop impact strength.

Abstract: According to an exemplary embodiment of the present disclosure, disclosed is an aluminum coated blank that includes a first coated steel sheet; a second coated steel sheet connected to the first coated steel sheet; and a joint portion that connects the first coated steel sheet to the second coated steel plate at a boundary between the first coated steel sheet and the second coated steel sheet.

Abstract: A method in which a high-quality packet telephony terminal apparatus performing low-latency and lossless packet communication with a counterpart packet telephony terminal apparatus operates in an integrated network structure in which a time sensitive network (TSN) and a packet communication network are combined may be disclosed. The packet telephony terminal apparatus may perform packet telephony call processing, perform a TSN stream reservation procedure when the counterpart packet telephony terminal apparatus is capable of performing a TSN function for lossless packet communication, adjust a size of a dejitter buffer when the TSN stream reservation procedure is successful, and perform low-latency packet telephony communication through the minimized size of the dejitter buffer.

Abstract: A battery pack is advantageous for effective control and maintenance of thermal events. A battery pack according to one aspect of the present disclosure may include a battery module having one or more battery cells; a fire extinguishing tank holding a fire extinguishing liquid, disposed on top of the battery module and having a through hole formed therein; and a cover member installed in the through hole of the fire extinguishing tank and configured to open or close the through hole according to a change in internal pressure of the fire extinguishing tank.

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

Abstract: An olefin polymer and a preparation method for manufacturing the olefin polymer are disclosed. The olefin polymer has a high melting point and a high crystallization temperature, thus having excellent heat resistance. Therefore, the olefin polymer may be utilized in spout pouches for high-temperature liquid containers, or the like. The olefin polymer may have a density of 0.9 to 0.95 g/cm3, preferably 0.91 to 0.945 g/cm3, and satisfies the following Equations 1a and 2a: 224.02×d?86.257<Tm, and ??[Equation 1a] 219.64×d?95.767<Tc.

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, and a first transistor of a first conductivity type over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel, and a first gate electrode around the first semiconductor channel. In an embodiment, the semiconductor device further comprises a second transistor of a second conductivity type above the first transistor. The second transistor comprises a second semiconductor channel, and a second gate electrode around the second semiconductor channel. In an embodiment, the second gate electrode and the first gate electrode comprise different materials.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, and a first transistor of a first conductivity type over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel, and a first gate electrode around the first semiconductor channel. In an embodiment, the semiconductor device further comprises a second transistor of a second conductivity type above the first transistor. The second transistor comprises a second semiconductor channel, and a second gate electrode around the second semiconductor channel. In an embodiment, the second gate electrode and the first gate electrode comprise different materials.

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

Abstract: The present invention relates to a melittin-anticancer drug conjugate in which melittin and an anticancer drug are conjugated, and to a method of preparing a melittin-anticancer drug conjugate by connecting melittin and an anticancer drug. A conjugate of the present invention is an anticancer material for targeting M2-type tumor-associated macrophages (TAM) and exhibits an excellent effect of selectively selecting M2-type tumor-associated macrophages (TAM), and thus may be used for a use of drug delivery for targeting M2-type tumor-associated macrophages.

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

Abstract: The present invention relates to a melittin-anticancer drug conjugate in which melittin and an anticancer drug are conjugated, and to a method of preparing a melittin-anticancer drug conjugate by connecting melittin and an anticancer drug. A conjugate of the present invention is an anticancer material for targeting M2-type tumor-associated macrophages (TAM) and exhibits an excellent effect of selectively selecting M2-type tumor-associated macrophages (TAM), and thus may be used for a use of drug delivery for targeting M2-type tumor-associated macrophages.