Abstract: A network communication device includes a plurality of ports, a memory, and a processor. The plurality of ports is configured to receive a packet. A memory is configured to store a first lookup table and a second lookup table. An entry of the first lookup table includes a flag field. An entry of the second lookup table includes an entry address of the first lookup table. The processor is coupled to the memory and the plurality of ports. The network communication device is configured to: analyze the packet by a software or hardware to obtain a source Media Access Control (MAC) address; obtain, according to the source MAC address of the packet, the entry of the first lookup table; read the flag field of the entry; and determine, according to the flag field, whether the entry is referred by the second lookup table.

Abstract: A test circuit for testing an integrated circuit includes a plurality of normal flip flops and a modified flip flop, wherein the integrated circuit includes a black box circuit and a plurality of combinational logic circuits. The normal flip flops each includes a first input pin, a second input pin and a first output pin and is configured to temporarily store the input value of the first input pin or the input value of the second input pin according to a scan enable signal. The modified flip flop includes a third input pin, a fourth input pin and a second output pin which are coupled to the black box circuit, the normal flip flops and the combinational logic circuits and is configured to temporarily store the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal.

Abstract: A test circuit for testing an integrated circuit includes a plurality of normal flip flops and a modified flip flop, wherein the integrated circuit includes a black box circuit and a plurality of combinational logic circuits. The normal flip flops each includes a first input pin, a second input pin and a first output pin and is configured to temporarily store the input value of the first input pin or the input value of the second input pin according to a scan enable signal. The modified flip flop includes a third input pin, a fourth input pin and a second output pin which are coupled to the black box circuit, the normal flip flops and the combinational logic circuits and is configured to temporarily store the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal.

Abstract: A circuitry applied in a network device is disclosed. The circuitry includes multiple ports, a processor port, a packet buffer, a control circuit and a parser, where the processor port is coupled to a memory and a processor via a bus. In operations of the circuitry, the packet buffer stores a packet received from one of the multiple ports. The parser analyzes the packet to determine a processing manner of the packet, and when the parser determines that the packet is to be processed by software, the control circuit delivers contents of the packet to the memory via the processor port in multiple segments or all at once, for software analysis executed by the processor.

Abstract: A data communication and processing method of a master device and a slave device is provided, wherein the method includes the steps of: using the master device to transmit a frame to the slave device via a communication medium, wherein the frame includes a plurality of fields, the plurality of fields includes a bursting size field and a data field, and contents within the bursting size field indicate a data amount of the data field; and using the slave device to receive the frame and store contents of the data field, or output data to the data field according to the data amount indicated by the contents within the bursting size field of the frame. In addition, a method for replacing preamble bits with a postamble bit to improve transmission efficiency is provided.

Abstract: A network communication device includes a plurality of ports, a memory, and a processor. The plurality of ports is configured to receive a packet. A memory is configured to store a first lookup table and a second lookup table. An entry of the first lookup table includes a flag field. An entry of the second lookup table includes an entry address of the first lookup table. The processor is coupled to the memory and the plurality of ports. The network communication device is configured to: analyze the packet by a software or hardware to obtain a source Media Access Control (MAC) address; obtain, according to the source MAC address of the packet, the entry of the first lookup table; read the flag field of the entry; and determine, according to the flag field, whether the entry is referred by the second lookup table.

Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an I/O interface circuit. The control circuit is electrically connected to a test machine, and is configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to propagate a scan test signal sended from the test machine to the scan chain circuit. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to propagate a response signal generated by the circuit under test to the test machine.

Abstract: A circuit having multiple scan modes is disclosed. The circuit includes a first circuit block and a second circuit block. The first circuit block corresponds to a first scan mode of the multiple scan modes, and the first circuit block includes at least one first scan chain for receiving a test signal from an external automatic test equipment. The second circuit block corresponds to a second scan mode of the multiple scan modes, and the second circuit block includes at least one second scan chain for receiving another test signal from the external automatic test equipment. The second scan chain includes at least one specific flip-flop positioned in the first circuit block, and the specific flip-flop is configured to drive the second circuit block.

Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an interface circuit. The control circuit is electrically connected to a test machine, and configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to conduct the scan chain circuit to the test machine. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to conduct the circuit under test to the test machine so as to propagate a response signal generated by the circuit under test to the test machine.

Abstract: A data communication and processing method of a master device and a slave device is provided, wherein the method includes the steps of: using the master device to transmit a frame to the slave device via a communication medium, wherein the frame includes a plurality of fields, the plurality of fields includes a bursting size field and a data field, and contents within the bursting size field indicate a data amount of the data field; and using the slave device to receive the frame and store contents of the data field, or output data to the data field according to the data amount indicated by the contents within the bursting size field of the frame. In addition, a method for replacing preamble bits with a postamble bit to improve transmission efficiency is provided.

Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an interface circuit. The control circuit is electrically connected to a test machine, and configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to conduct the scan chain circuit to the test machine. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to conduct the circuit under test to the test machine so as to propagate a response signal generated by the circuit under test to the test machine.

Abstract: The present disclosure relates to a circuit testing system, including a control circuit and an I/O interface circuit. The control circuit is electrically connected to a test machine, and is configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to propagate a scan test signal sended from the test machine to the scan chain circuit. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to propagate a response signal generated by the circuit under test to the test machine.

Abstract: A circuit applied to multiple scan modes is disclosed, wherein the circuit can increase fault coverage during chip testing without using scan chain wrappers. The circuit includes a first circuit block and a second circuit block. The first circuit block corresponds to a first scan mode of the multiple scan modes, and the first circuit block includes at least one first scan chain for receiving a test signal from an external automatic test equipment. The second circuit block corresponds to a second scan mode of the multiple scan modes, and the second circuit block includes at least one second scan chain for receiving another test signal from the external automatic test equipment. The second scan chain includes at least one specific flip-flop positioned in the first circuit block, and the specific flip-flop is configured to drive the second circuit block.

Abstract: This invention provides traffic monitoring ports of a network switch which are control gates, each connected with a port of the network switch. The control gates also connect with a monitoring bus, and a configuration bus. The users can apply the control gates to dominate the traffic direction via the configuration bus, using the monitoring bus to transfer communication materials. This makes the traffic of any port monitored by the other port. This invention provides users with a simply operated network monitoring function, and a completed function of the monitoring port.