Abstract: Disclosed herein is a series-type dye-sensitized solar cell module. The series-type dye-sensitized solar cell module includes a plurality of solar cell unit cells having working electrodes and a counter electrode, a plurality of printed circuit boards having insulation body portions, each having a first current carrying portion which comes into contact with the working electrode of each solar cell unit cell on one surface of each insulation body portion so that an electric current is applied thereto, and a second current carrying portion which comes into contact with the counter electrode of the solar cell unit cells on the other surface of the insulation body portion so that an electric current is applied thereto, and at least one connection terminal portion which electrically connects the first current carrying portion of one printed circuit board to the second current carrying portion of another printed circuit board adjacent thereto.

Abstract: The present invention relates to a method of sealing a dye-sensitized solar cell, which seals a dye-sensitized solar cell module filled and sealed with an electrolyte therein by surrounding the outer side of the solar cell module. The method includes: a dipping step of dipping the solar cell module into a liquid-state sealing agent; and a hardening step of forming a sealer on the outer side of the solar cell module by hardening the liquid-state sealing agent, with the solar cell module dipped therein, and so it is possible to achieve complete sealing so that an air pocket inside a solar cell module is not formed.

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a substrate and a MOS transistor formed on the substrate. The MOS transistor includes a first gate insulating layer formed on the substrate, a second gate insulating layer formed on one side of the first gate insulating layer and having a thickness thicker than that of the first gate insulating layer, a gate electrode formed on the first gate insulating layer and the second gate insulating layer, a source region adjacent to the first gate insulating layer, and a drain region adjacent to the second gate insulating layer.