Abstract: A nonvolatile semiconductor memory device comprising an array of cell units, each cell unit including at least one memory transistor which has a floating gate and a control gate, the array being divided into a plurality of memory blocks each having a certain number of cell units. A selected memory block is erased by an erase voltage applied to a semiconductor substrate while unselected memory blocks are prevented from erasing by capacitive coupling of the erase voltage to floated word lines connected to control gates of memory transistors of the unselected memory blocks. In a program mode where a program voltage is applied to a selected word line of a selected memory block and a pass voltage is applied to unselected word lines of the selected memory block, channel regions and source and drain junctions of memory transistors of cell units in the selected memory block are charged to a program inhibition voltage.

Abstract: A nonvolatile semiconductor memory device according to the present invention includes an array of cell units, each cell unit including at least one memory transistor which has a floating gate and a control gate, the array being divided into a plurality of memory blocks each having a certain number of cell units. The nonvolatile semiconductor memory device operates in a program mode, a program verify mode and a read mode. A current source provides a predetermined electrical current to the bit lines during both data reading and programming modes, and a common data latch stores program data during a write operation, as well as senses and stores data when the nonvolatile memory device is operated in a data read mode and a program verify mode.

Abstract: A nonvolatile semiconductor memory device comprising an array of cell units, each cell unit including at least one memory transistor which has a floating gate and a control gate, the array being divided into a plurality of memory blocks each having a certain number of cell units. A selected memory block is erased by an erase voltage applied to a semiconductor substrate while unselected memory blocks are prevented from erasing by capacitive coupling of the erase voltage to floated word lines connected to control gates of memory transistors of the unselected memory blocks. In a program mode where a program voltage is applied to a selected word line of a selected memory block and a pass voltage is applied to unselected word lines of the selected memory block, channel regions and source and drain junctions of memory transistors of cell units in the selected memory block are charged to a program inhibition voltage.