Patents by Inventor Jeong-hee Chung

Jeong-hee Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7314806
    Abstract: A metal-oxy-nitride seed dielectric layer can be formed on a metal-nitride lower electrode of a metal-insulator-metal (MIM) type capacitor. The metal-oxy-nitride seed dielectric layer can act as a barrier layer to reduce a reaction with the metal-nitride lower electrode during, for example, backend processing used to form upper levels of metallization/structures in an integrated circuit including the MIM type capacitor. Nitrogen included in the metal-oxy-nitride seed dielectric layer can reduce the type of reaction, which may occur in conventional type MIM capacitors. A metal-oxide main dielectric layer can be formed on the metal-oxy-nitride seed dielectric layer and can remain separate from the metal-oxy-nitride seed dielectric layer in the MIM type capacitor. The metal-oxide main dielectric layer can be stabilized (using, for example, a thermal or plasma treatment) to remove defects (such as carbon) therefrom and to adjust the stoichiometry of the metal-oxide main dielectric layer.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: January 1, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hyoung Choi, Sung-tae Kim, Ki-chul Kim, Cha-young Yoo, Jeong-hee Chung, Se-hoon Oh, Jeong-sik Choi
  • Patent number: 7201943
    Abstract: A thin film is formed using an atomic layer deposition process, by introducing a first reacting material including tantalum precursors and titanium precursors onto a substrate. A portion of the first reacting material is chemisorbed onto the substrate. Then, a second reacting material including oxygen is introduced onto the substrate. A portion of the second reacting material is also chemisorbed onto the substrate, to form an atomic layer of a solid material on the substrate. The solid material may be used as a dielectric layer of the capacitor and/or a gate dielectric layer of the transistor.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: April 10, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Sung Park, Jeong-Hee Chung, Jae-Hyun Yeo
  • Publication number: 20050227432
    Abstract: A metal-oxy-nitride seed dielectric layer can be formed on a metal-nitride lower electrode of a meta-insulator-metal (MIM) type capacitor. The metal-oxy-nitride seed dielectric layer can act as a barrier layer to reduce a reaction with the metal-nitride lower electrode during, for example, backend processing used to form upper levels of metallization/structures in an integrated circuit including the MIM type capacitor. Nitrogen included in the metal-oxy-nitride seed dielectric layer can reduce the type of reaction, which may occur in conventional type MIM capacitors. A metal-oxide main dielectric layer can be formed on the metal-oxy-nitride seed dielectric layer and can remain separate from the metal-oxy-nitride seed dielectric layer in the MIM type capacitor. The metal-oxide main dielectric layer can be stabilized (using, for example, a thermal or plasma treatment) to remove defects (such as carbon) therefrom and to adjust the stoichiometry of the metal-oxide main dielectric layer.
    Type: Application
    Filed: April 1, 2005
    Publication date: October 13, 2005
    Inventors: Jae-hyoung Choi, Sung-tae Kim, Ki-chul Kim, Cha-young Yoo, Jeong-hee Chung, Se-hoon Oh, Jeong-sik Choi
  • Patent number: 6919243
    Abstract: An integrated circuit capacitor is manufactured by forming a lower electrode on a substrate and forming a metal preprocessed layer on the lower electrode using chemical vapor deposition in which a metal precursor is used as a source gas and the metal precursor comprises oxygen. A dielectric layer is then formed on the metal preprocessed layer and an upper electrode is formed on the dielectric layer. The metal preprocessed layer may reduce oxidation of the lower electrode due to oxygen supplied during formation of the dielectric layer.
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: July 19, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-hee Chung, In-sung Park, Jae-hyun Yeo
  • Patent number: 6893501
    Abstract: A method for manufacturing a capping layer covering a capacitor of a semiconductor memory device, preferably a metal-insulator-metal (MIM) capacitor, wherein the method includes forming a capacitor having a lower electrode, a dielectric layer and an upper electrode on a semiconductor substrate, forming a capping layer on the capacitor, and crystallizing the dielectric layer. Here, forming the capping layer includes stabilizing for deposition of the capping layer without providing oxygen gas, depositing the capping layer by providing a reaction source for the capping layer; and purging an inside of a reactor for forming the capping layer.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: May 17, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-chul Kim, Sung-tae Kim, Young-sun Kim, Jeong-hee Chung, Wan-don Kim, Yun-jung Lee, Han-mei Choi
  • Patent number: 6884675
    Abstract: Semiconductor capacitors comprise first electrodes, second electrodes, and tantalum oxide layers positioned between the first electrodes and the second electrodes. The tantalum oxide layers are formed by depositing at least one precursor and ozone gas, the at least one precursor represented by the formula: wherein X is selected from the group consisting of nitrogen, sulfur, oxygen, and a carbonyl group; and wherein R1 and R2 are independently alkyl.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: April 26, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-hee Chung, In-sung Park, Jae-hyun Yeo
  • Publication number: 20050026078
    Abstract: A method for forming a fine pattern in a semiconductor substrate, by coating a target layer to be etched on a semiconductor substrate with a resist composition including at least one compound capable of forming a photoresist pattern by a photolithography process, and a free radical initiator. The free radical initiator is capable of being decomposed by a thermal process at a temperature equal to or higher than the glass transition temperature of the at least one compound. A lithography process is performed on the resist compound layer to form a photoresist pattern. The resist compound layer having the photoresist pattern formed therein is heated to a temperature equal to or higher than the glass transition temperature of the at least one compound, and wherein a partial cross-linking reaction in the resist composition occurs.
    Type: Application
    Filed: August 24, 2004
    Publication date: February 3, 2005
    Inventors: Sang-jun Choi, Yool Kang, Joo-tae Moon, Jeong-hee Chung, Sang-gyun Woo
  • Patent number: 6803176
    Abstract: A method for forming a fine pattern in a semiconductor substrate, by coating a target layer to be etched on a semiconductor substrate with a resist composition including at least one compound capable of forming a photoresist pattern by a photolithography process, and a free radical initiator. The free radical initiator is capable of being decomposed by a thermal process at a temperature equal to or higher than the glass transition temperature of the at least one compound. A lithography process is performed on the resist compound layer to form a photoresist pattern. The resist compound layer having the photoresist pattern formed therein is heated to a temperature equal to or higher than the glass transition temperature of the at least one compound, and wherein a partial cross-linking reaction in the resist composition occurs.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: October 12, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-jun Choi, Yool Kang, Joo-tae Moon, Jeong-hee Chung, Sang-gyun Woo
  • Publication number: 20040180493
    Abstract: Semiconductor capacitors comprise first electrodes, second electrodes, and tantalum oxide layers positioned between the first electrodes and the second electrodes.
    Type: Application
    Filed: March 25, 2004
    Publication date: September 16, 2004
    Inventors: Jeong-hee Chung, In-sung Park, Jae-hyun Yeo
  • Patent number: 6734480
    Abstract: A semiconductor capacitor comprising: a first electrode; a second electrode; and a tantalum oxide layer positioned between said first electrode and said second electrodes. The tantalum oxide layer formed by depositing at least one precursor and ozone gas, the at least one precursor represented by the formula: wherein X is selected from the group consisting of nitrogen, sulfur, oxygen, and a carbonyl group; and wherein R1 and R2 are independently alkyl.
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: May 11, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-hee Chung, In-sung Park, Jae-hyun Yeo
  • Publication number: 20040018307
    Abstract: A thin film is formed using an atomic layer deposition process, by introducing a first reacting material including tantalum precursors and titanium precursors onto a substrate. A portion of the first reacting material is chemisorbed onto the substrate. Then, a second reacting material including oxygen is introduced onto the substrate. A portion of the second reacting material is also chemisorbed onto the substrate, to form an atomic layer of a solid material on the substrate. The solid material may be used as a dielectric layer of the capacitor and/or a gate dielectric layer of the transistor.
    Type: Application
    Filed: February 21, 2003
    Publication date: January 29, 2004
    Inventors: In-Sung Park, Jeong-Hee Chung, Jae-Hyun Yeo
  • Publication number: 20030183153
    Abstract: A method for manufacturing a capping layer covering a capacitor of a semiconductor memory device, preferably a metal-insulator-metal (MIM) capacitor, wherein the method includes forming a capacitor having a lower electrode, a dielectric layer and an upper electrode on a semiconductor substrate, forming a capping layer on the capacitor, and crystallizing the dielectric layer. Here, forming the capping layer includes stabilizing for deposition of the capping layer without providing oxygen gas, depositing the capping layer by providing a reaction source for the capping layer; and purging an inside of a reactor for forming the capping layer.
    Type: Application
    Filed: December 17, 2002
    Publication date: October 2, 2003
    Inventors: Ki-Chul Kim, Sung-Tae Kim, Young-Sun Kim, Jeong-Hee Chung, Wan-Don Kim, Yun-Jung Lee, Han-Mei Choi
  • Publication number: 20030054292
    Abstract: A method for forming a fine pattern in a semiconductor substrate, by coating a target layer to be etched on a semiconductor substrate with a resist composition including at least one compound capable of forming a photoresist pattern by a photolithography process, and a free radical initiator. The free radical initiator is capable of being decomposed by a thermal process at a temperature equal to or higher than the glass transition temperature of the at least one compound. A lithography process is performed on the resist compound layer to form a photoresist pattern. The resist compound layer having the photoresist pattern formed therein is heated to a temperature equal to or higher than the glass transition temperature of the at least one compound, and wherein a partial cross-linking reaction in the resist composition occurs.
    Type: Application
    Filed: August 23, 2002
    Publication date: March 20, 2003
    Inventors: Sang-Jun Choi, Yool Kang, Joo-Tae Moon, Jeong-Hee Chung, Sang-Gyun Woo
  • Patent number: 6485895
    Abstract: A method for forming a fine pattern in a semiconductor substrate, comprises the steps of (a) coating a target layer to be etched on a semiconductor substrate with a resist composition comprising at least one compound capable of forming a photoresist pattern by a photolithography process, and a free radical initiator, wherein the free radical initiator is one which is capable of being decomposed by a thermal process at a temperature equal to or higher than the glass transition temperature of the at least one compound, wherein said coating step results in forming a resist compound layer comprising the resist composition; (b) performing a lithography process on the resist compound layer to form a photoresist pattern of at least one opening having a first width, wherein the target layer is exposed through the first width; and (c) heating the resist compound layer having the photoresist pattern formed therein to a temperature equal to or higher than the glass transition temperature of the at least one compound, an
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: November 26, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-jun Choi, Yool Kang, Joo-tae Moon, Jeong-hee Chung, Sang-gyun Woo
  • Publication number: 20020140005
    Abstract: Semiconductor capacitors comprise first electrodes, second electrodes, and tantalum oxide layers positioned between the first electrodes and the second electrodes.
    Type: Application
    Filed: January 15, 2002
    Publication date: October 3, 2002
    Inventors: Jeong-Hee Chung, In-Sung Park, Jae-Hyun Yeo
  • Publication number: 20020094634
    Abstract: An integrated circuit capacitor is manufactured by forming a lower electrode on a substrate and forming a metal preprocessed layer on the lower electrode using chemical vapor deposition in which a metal precursor is used as a source gas and the metal precursor comprises oxygen. A dielectric layer is then formed on the metal preprocessed layer and an upper electrode is formed on the dielectric layer. The metal preprocessed layer may reduce oxidation of the lower electrode due to oxygen supplied during formation of the dielectric layer.
    Type: Application
    Filed: January 9, 2002
    Publication date: July 18, 2002
    Inventors: Jeong-hee Chung, In-sung Park, Jae-hyun Yeo