Patents by Inventor Jeong-hee Han
Jeong-hee Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240255376Abstract: The present invention relates to a shock test apparatus for pouch-shaped battery cells and a shock test method for pouch-shaped battery cells using the same, and more particularly to a shock test apparatus for pouch-shaped battery cells, the shock test apparatus including a flat bottom plate, a jig including a first jig member and a second jig member located respectively at opposite surfaces of a pouch-shaped battery cell, each of the first jig member and the second jig member having a quadrangular shape, and a pressing member configured to press a predetermined part of the pouch-shaped battery cell, and a shock test method for pouch-shaped battery cells using the same.Type: ApplicationFiled: December 7, 2022Publication date: August 1, 2024Applicant: LG Energy Solution, Ltd.Inventors: Jeong Hee Han, Kyu Sang Cho, Hyun Tae Kim
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Patent number: 9687545Abstract: Disclosed are a nonspecific immunostimulant composition, a preparation method thereof, and uses thereof. The composition includes 150 to 300 wt. parts of sodium silicate, 2˜8 wt. parts of sodium thiosulfate, 0.5˜2 wt. parts of sodium carbonate, 0.5˜2 wt. parts of potassium chloride, 200˜400 wt. parts of white sugar, and 300˜400 wt. parts of water, based on 100 wt. parts of potassium carbonate. The composition exhibits excellent defense against the mortality caused by AIV H5N1, thus improving the survival of infected animals. As a supplement of a formulated feed mixture for farmed aquatic organisms, the composition provides excellent immunostimulation and disease resistance so as to decrease the mass mortality of aquatic organisms and to increase productivity. Particularly, when raised with a food in mixture with the composition, livestock and farmed aquatic organisms are immunologically improved so that they can endure and are protected against epidemic diseases caused by viruses and bacteria.Type: GrantFiled: February 20, 2015Date of Patent: June 27, 2017Assignee: BARODON-S.F.CORP.Inventors: Soo-il Choi, Hyun Suk Choi, Yun Jeong Choi, Kyung Ae Hong, Byung Woo Yoo, Yong Ho Park, Sun Young Hwang, Jeong Hee Han, Chang Hoon Shin
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Publication number: 20150238599Abstract: Disclosed are a nonspecific immunostimulant composition, a preparation method thereof, and uses thereof. The composition includes 150 to 300 wt. parts of sodium silicate, 2˜8 wt. parts of sodium thiosulfate, 0.5˜2 wt. parts of sodium carbonate, 0.5˜2 wt. parts of potassium chloride, 200˜400 wt. parts of white sugar, and 300˜400 wt. parts of water, based on 100 wt. parts of potassium carbonate. The composition exhibits excellent defense against the mortality caused by AIV H5N1, thus improving the survival of infected animals. As a supplement of a formulated feed mixture for farmed aquatic organisms, the composition provides excellent immunostimulation and disease resistance so as to decrease the mass mortality of aquatic organisms and to increase productivity. Particularly, when raised with a food in mixture with the composition, livestock and farmed aquatic organisms are immunologically improved so that they can endure and are protected against epidemic diseases caused by viruses and bacteria.Type: ApplicationFiled: February 20, 2015Publication date: August 27, 2015Inventors: Soo-il CHOI, Hyun Suk CHOI, Yun Jeong CHOI, Kyung Ae HONG, Byung Woo YOO, Yong Ho PARK, Sun Young HWANG, Jeong Hee HAN, Chang Hoon SHIN
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Patent number: 9048329Abstract: An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.Type: GrantFiled: September 12, 2013Date of Patent: June 2, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Young Kim, Kang L. Wang, Yong-Jik Park, Jeong-Hee Han, Augustin Jinwoo Hong
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Patent number: 9048307Abstract: A semiconductor device having reduced leakage current and increased capacitance without increasing an equivalent oxide thickness (EOT) can be manufactured by a method that includes providing a substrate having a dummy gate pattern; forming a gate forming trench by removing the dummy gate pattern; forming a stacked insulation layer within the gate forming trench, wherein the forming of the stacked insulation layer includes forming a first high-k dielectric layer, forming a second high-k dielectric layer by performing heat treatment on the first high-k dielectric layer, and, after the heat treatment, forming a third high-k dielectric layer on the second high-k dielectric layer, the third high-k dielectric layer having a higher relative permittivity than the second high-k dielectric layer and having a dielectric constant of 40 or higher; and forming a gate electrode within the gate forming trench.Type: GrantFiled: June 14, 2012Date of Patent: June 2, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Yeol Song, Jeong-Hee Han, Sang-Jin Hyun, Hyeok-Jun Son, Sung-Kee Han
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Publication number: 20140246726Abstract: A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.Type: ApplicationFiled: May 12, 2014Publication date: September 4, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Hoon-Joo NA, Hyung-Seok HONG, Sang-Bom KANG, Hyeok-Jun SON, June-Hee LEE, Jeong-Hee HAN, Sang-Jin HYUN
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Patent number: 8748251Abstract: A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.Type: GrantFiled: June 20, 2012Date of Patent: June 10, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hoon-Joo Na, Hyung-Seok Hong, Sang-Bom Kang, Hyeok-Jun Son, June-Hee Lee, Jeong-Hee Han, Sang-Jin Hyun
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Patent number: 8664707Abstract: Provided is a semiconductor device that can include a lower interconnection on a substrate and at least one upper interconnection disposed on the lower interconnection. At least one gate structure can be disposed between the upper interconnection and the lower interconnection, where the gate structure can include a plurality of gate lines that are vertically stacked so that each of the gate lines has a wiring portion that is substantially parallel to an upper surface of the substrate and a contact portion that extends from the wiring portion along a direction penetrating an upper surface of the substrate. At least one semiconductor pattern can connect the upper and lower interconnections.Type: GrantFiled: March 23, 2012Date of Patent: March 4, 2014Assignees: Samsung Electronics Co., Ltd., The Regents of the University of CaliforniaInventors: Ji-Young Kim, Kang L. Wang, Yong-Jik Park, Jeong-Hee Han, Augustin Jinwoo Hong
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Publication number: 20140015032Abstract: An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.Type: ApplicationFiled: September 12, 2013Publication date: January 16, 2014Inventors: Ji-Young Kim, Kang L. Wang, Yong-Jik Park, Jeong-Hee Han, Augustin Jinwoo Hong
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Patent number: 8580629Abstract: A method of fabricating a semiconductor device may include: preparing a substrate in which first and second regions are defined; forming an interlayer insulating film, which includes first and second trenches, on the substrate; forming a work function control film, which contains Al and N, along a top surface of the interlayer insulating film, side and bottom surfaces of the first trench, and side and bottom surfaces of the second trench; forming a mask pattern on the work function control film formed in the second region; injecting a work function control material into the work function control film formed in the first region to control a work function of the work function control film formed in the first region; removing the mask pattern; and forming a first metal gate electrode to fill the first trench and forming a second metal gate electrode to fill the second trench.Type: GrantFiled: September 23, 2011Date of Patent: November 12, 2013Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Hong-Bae Park, Sang-Jin Hyun, Hu-Yong Lee, Hoon-Joo Na, Jeong-Hee Han, Hye-Lan Lee, Hyung-Seok Hong
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Patent number: 8541832Abstract: An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.Type: GrantFiled: June 16, 2010Date of Patent: September 24, 2013Assignees: Samsung Electronics Co., Ltd., The Regents of the University of CaliforniaInventors: Ji-Young Kim, Kang L. Wang, Yong-Jik Park, Jeong-Hee Han, Augustin Jinwoo Hong
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Publication number: 20120329262Abstract: A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.Type: ApplicationFiled: June 20, 2012Publication date: December 27, 2012Inventors: Hoon-Joo NA, Hyung-Seok Hong, Sang-Bom Kang, Hyeok-Jun Son, June-Hee Lee, Jeong-Hee Han, Sang-Jin Hyun
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Publication number: 20120319216Abstract: A semiconductor device having reduced leakage current and increased capacitance without increasing an equivalent oxide thickness (EOT) can be manufactured by a method that includes providing a substrate having a dummy gate pattern; forming a gate forming trench by removing the dummy gate pattern; forming a stacked insulation layer within the gate forming trench, wherein the forming of the stacked insulation layer includes forming a first high-k dielectric layer, forming a second high-k dielectric layer by performing heat treatment on the first high-k dielectric layer, and, after the heat treatment, forming a third high-k dielectric layer on the second high-k dielectric layer, the third high-k dielectric layer having a higher relative permittivity than the second high-k dielectric layer and having a dielectric constant of 40 or higher; and forming a gate electrode within the gate forming trench.Type: ApplicationFiled: June 14, 2012Publication date: December 20, 2012Inventors: Jae-Yeol Song, Jeong-Hee Han, Sang-Jin Hyun, Hyeok-Jun Son, Sung-Kee Han
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Publication number: 20120196433Abstract: Provided is a manufacturing method for a semiconductor device having reduced leakage current and increased capacitance while improving interface characteristics. The manufacturing method includes forming a silicon oxide layer on a base layer including silicon, forming a silicon oxynitride layer by implanting nitrogen into the silicon oxide layer, and forming hydroxy groups on a surface of the silicon oxynitride layer while etching the silicon oxynitride layer.Type: ApplicationFiled: August 12, 2011Publication date: August 2, 2012Inventors: Jeong-Hee Han, Hyeok-Jun Son, Sang-Jin Hyun, Hoon-Joo Na
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Publication number: 20120181593Abstract: Provided is a semiconductor device that can include a lower interconnection on a substrate and at least one upper interconnection disposed on the lower interconnection. At least one gate structure can be disposed between the upper interconnection and the lower interconnection, where the gate structure can include a plurality of gate lines that are vertically stacked so that each of the gate lines has a wiring portion that is substantially parallel to an upper surface of the substrate and a contact portion that extends from the wiring portion along a direction penetrating an upper surface of the substrate. At least one semiconductor pattern can connect the upper and lower interconnections.Type: ApplicationFiled: March 23, 2012Publication date: July 19, 2012Inventors: Ji-Young Kim, Kang L. Wang, Yong-Jik Park, Jeong-Hee Han, Augustin Jinwoo Hong
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Publication number: 20120122309Abstract: A method of fabricating a semiconductor device may include: preparing a substrate in which first and second regions are defined; forming an interlayer insulating film, which includes first and second trenches, on the substrate; forming a work function control film, which contains Al and N, along a top surface of the interlayer insulating film, side and bottom surfaces of the first trench, and side and bottom surfaces of the second trench; forming a mask pattern on the work function control film formed in the second region; injecting a work function control material into the work function control film formed in the first region to control a work function of the work function control film formed in the first region; removing the mask pattern; and forming a first metal gate electrode to fill the first trench and forming a second metal gate electrode to fill the second trench.Type: ApplicationFiled: September 23, 2011Publication date: May 17, 2012Applicant: Samsung Electronics Co., Ltd.Inventors: Hong-Bae PARK, Sang-Jin Hyun, Hu-Yong Lee, Hoon-Joo Na, Jeong-Hee Han, Hye-Lan Lee, Hyung-Seok Hong
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Patent number: 8164134Abstract: Provided are a semiconductor device and a method of fabricating the same. At least one mold structure defining at least one first opening is formed on a substrate, wherein the mold structure comprises first mold patterns and second mold patterns that are sequentially and alternatingly stacked. Thereafter, side surfaces of the first mold patterns are selectively etched to form undercut regions between the second mold patterns. Then, a semiconductor layer is formed to cover a surface of the mold structure where the undercut regions are formed, and gate patterns are formed, which fill respective undercut regions where the semiconductor layer is formed.Type: GrantFiled: June 9, 2009Date of Patent: April 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Young Kim, Kang L. Wang, Yong-Jik Park, Jeong-Hee Han, Augustin Jinwoo Hong
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Publication number: 20110237055Abstract: A stacked semiconductor device that is reliable by forming an insulating layer on a lower memory layer and by forming a single crystalline semiconductor in portions of the insulating layer. A method of manufacturing the stacked semiconductor device, including: providing a lower memory layer including a plurality of lower memory structures; forming an insulating layer on the lower memory layer; forming trenches by removing portions of the insulating layer; forming a preparatory semiconductor layer for filling the trenches; and forming a single crystalline semiconductor layer by phase-changing the preparatory semiconductor layer.Type: ApplicationFiled: March 22, 2011Publication date: September 29, 2011Inventors: Yong-hoon Son, Si-Young Choi, Myoung-Bum Lee, Ki-Hyun Hwang, Seung-Jae Baik, Jeong Hee Han
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Publication number: 20110018051Abstract: An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.Type: ApplicationFiled: June 16, 2010Publication date: January 27, 2011Inventors: Ji-Young Kim, Kang L. Wang, Yong-Jik Park, Jeong-Hee Han, Augustin Jinwoo Hong
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Patent number: 7858464Abstract: Methods of manufacturing non-volatile memory devices that can reduce or prevent loss of charges stored in a charge storage layer and/or that can improve charge storage capacity by neutral beam irradiation of an insulating layer are disclosed. The methods include forming a tunneling insulating layer on a substrate, forming a charge storage layer on the tunneling insulating layer, forming a blocking insulating layer on the charge storage layer, irradiating the blocking insulating layer and/or the tunneling insulating layer with a neutral beam, and forming a gate conductive layer on the blocking insulating layer.Type: GrantFiled: December 31, 2008Date of Patent: December 28, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-doo Chae, Chung-woo Kim, Choong-man Lee, Yung-hee Lee, Chan-jin Park, Sung-wook Hwang, Jeong-hee Han, Do-haing Lee, Jin-seok Lee