Patents by Inventor Jeong Hee Oh

Jeong Hee Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6429055
    Abstract: Disclosed is a method for making an SOI MOSFET, which is capable of improving threshold voltage variations and a parasitic bipolar effect generated in the formation of fully depleted (FD) SOI semiconductor integrated circuits using a recess channel. The method involves the steps of forming a buried oxide film and an active silicon film over a silicon-on-insulator substrate, forming a channel at a recess channel, forming dummy spacers at opposite side walls of the etched active silicon film, forming a gate between the dummy spacers, forming a photoresist film on the gate and the active silicon film, forming lightly doped drain regions, removing the dummy spacers, forming lightly doped ion regions, respectively, forming spacers at opposite side walls of the recess channel region, respectively, removing the photoresist film, forming a source region and a drain region, forming source/drain electrodes and a gate electrode on the resultant structure.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: August 6, 2002
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jeong Hee Oh
  • Patent number: 6407427
    Abstract: The present invention discloses a SOI device capable of removing a floating body effect and improving a static electricity emission characteristic and a method of fabricating the same. The SOI device according to the present invention, comprising: a base substrate; a buried oxide layer formed to expose a predetermined region of the base substrate on the base substrate; a body contact layer formed to the same thickness as the buried oxide layer on the exposed base substrate region; a body layer of a transistor formed on the buried oxide layer and the body contact layer; a gate having a gate oxide layer formed on the body layer; and a drain region and a source region formed in a depth contacting with the buried oxide in the body layer region at both sides of the gate, the source being in contact with the body contact layer.
    Type: Grant
    Filed: November 6, 2000
    Date of Patent: June 18, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Jeong Hee Oh
  • Publication number: 20020009859
    Abstract: Disclosed is a method for making an SOI MOSFET, which is capable of improving threshold voltage variations and a parasitic bipolar effect generated in the formation of fully depleted (FD) SOI semiconductor integrated circuits using a recess channel. The method involves the steps of forming a buried oxide film and an active silicon film over a silicon-on-insulator substrate, forming a channel at a recess channel, forming dummy spacers at opposite side walls of the etched active silicon film, forming a gate between the dummy spacers, forming a photoresist film on the gate and the active silicon film, forming lightly doped drain regions, removing the dummy spacers, forming lightly doped ion regions, respectively, forming spacers at opposite side walls of the recess channel region, respectively, removing the photoresist film, forming a source region and a drain region, forming source/drain electrodes and a gate electrode on the resultant structure.
    Type: Application
    Filed: June 26, 2001
    Publication date: January 24, 2002
    Applicant: Hynix Semiconductor Inc.
    Inventor: Jeong Hee Oh