Abstract: A semiconductor device including a high-voltage isolation capacitor and a mixed-signal integrated circuit, wherein the high-voltage isolation capacitor includes bottom electrodes, each spaced apart from another, disposed on a substrate; top electrodes disposed on corresponding ones of the bottom electrodes; an inter-metal dielectric layer disposed between the bottom electrodes and the top electrodes; and low bandgap dielectric layers disposed on the inter-metal dielectric layer. Each of the low bandgap dielectric layers is disposed below corresponding ones of the top electrodes, and the low bandgap dielectric layers are absent in the mixed-signal integrated circuit.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes providing a high-voltage isolation capacitor region and a mixed-signal integrated circuit region on a substrate, forming a bottom electrode on the high-voltage isolation capacitor region, forming a bottom metal line on the mixed-signal integrated circuit region, forming an inter-metal dielectric layer on the bottom electrode and the bottom metal line, forming a top via in the inter-metal dielectric layer, forming a low bandgap dielectric layer on the top via and the inter-metal dielectric layer, patterning the low bandgap dielectric layer to form a patterned low bandgap dielectric layer, depositing a thick metal film on the top via and the patterned low bandgap dielectric layer, and patterning the thick metal film to form a top metal line on the high-voltage isolation capacitor region and form a top electrode on the mixed-signal integrated circuit region.

Abstract: A semiconductor device includes a substrate, the substrate includes a capacitor region and a metal wiring region. The capacitor region includes a lower electrode formed on the substrate, an interlayer insulating layer formed on the lower electrode, a dielectric layer pattern formed on the interlayer insulating layer, and an upper electrode formed on the dielectric layer pattern. The metal wiring region includes a lower metal wiring formed parallel to the lower electrode, the interlayer insulating layer formed on the lower metal wiring, an upper insulating layer formed on the interlayer insulating layer and having a thickness smaller than a thickness of the interlayer insulating layer, and an upper metal wiring formed on the upper insulating layer, and formed in parallel with the upper electrode. The upper insulating layer and the dielectric layer pattern are formed of different materials.