Abstract: A high voltage generating circuit is disclosed. In the high voltage generating circuit a boost node is precharged and boosted by a plurality of pump circuits and then discharged to an output terminal. Where a voltage apparent at the boost node is smaller than a power supply voltage, the voltage apparent at the boost node is elevated to the power supply voltage. Where the voltage apparent at the boost node is larger than the power supply voltage, a current path is prevented from forming between the boost node and the power supply voltage so as to maintain the voltage apparent at the boost node.

Abstract: A high voltage generating circuit is disclosed. In the high voltage generating circuit a boost node is precharged and boosted by a plurality of pump circuits and then discharged to an output terminal. Where a voltage apparent at the boost node is smaller than a power supply voltage, the voltage apparent at the boost node is elevated to the power supply voltage. Where the voltage apparent at the boost node is larger than the power supply voltage, a current path is prevented from forming between the boost node and the power supply voltage so as to maintain the voltage apparent at the boost node.

Abstract: A high voltage generating circuit is disclosed. In the high voltage generating circuit a boost node is precharged and boosted by a plurality of pump circuits and then discharged to an output terminal. Where a voltage apparent at the boost node is smaller than a power supply voltage, the voltage apparent at the boost node is elevated to the power supply voltage. Where the voltage apparent at the boost node is larger than the power supply voltage, a current path is prevented from forming between the boost node and the power supply voltage so as to maintain the voltage apparent at the boost node.

Abstract: A high voltage generating circuit is disclosed. In the high voltage generating circuit a boost node is precharged and boosted by a plurality of pump circuits and then discharged to an output terminal. Where a voltage apparent at the boost node is smaller than a power supply voltage, the voltage apparent at the boost node is elevated to the power supply voltage. Where the voltage apparent at the boost node is larger than the power supply voltage, a current path is prevented from forming between the boost node and the power supply voltage so as to maintain the voltage apparent at the boost node.

Abstract: A high voltage generating circuit is disclosed. In the high voltage generating circuit a boost node is precharged and boosted by a plurality of pump circuits and then discharged to an output terminal. Where a voltage apparent at the boost node is smaller than a power supply voltage, the voltage apparent at the boost node is elevated to the power supply voltage. Where the voltage apparent at the boost node is larger than the power supply voltage, a current path is prevented from forming between the boost node and the power supply voltage so as to maintain the voltage apparent at the boost node.

Abstract: A high voltage generating circuit is disclosed. In the high voltage generating circuit a boost node is precharged and boosted by a plurality of pump circuits and then discharged to an output terminal. Where a voltage apparent at the boost node is smaller than a power supply voltage, the voltage apparent at the boost node is elevated to the power supply voltage. Where the voltage apparent at the boost node is larger than the power supply voltage, a current path is prevented from forming between the boost node and the power supply voltage so as to maintain the voltage apparent at the boost node.

Abstract: A high voltage generating circuit is disclosed. In the high voltage generating circuit a boost node is precharged and boosted by a plurality of pump circuits and then discharged to an output terminal. Where a voltage apparent at the boost node is smaller than a power supply voltage, the voltage apparent at the boost node is elevated to the power supply voltage. Where the voltage apparent at the boost node is larger than the power supply voltage, a current path is prevented from forming between the boost node and the power supply voltage so as to maintain the voltage apparent at the boost node.

Abstract: A DRAM with a general interleaving scheme for data input/output uses a normal bank structure. The DRAM provides a high-performance without consideration of a data access pattern. In order to implement the high-performance, the DRAM includes a plurality of normal banks, at least one cache bank, which has the same data access scheme with the normal banks, for selectively storing data with a normal bank selected at a read mode and a controller for controlling the access to the cache bank and the selected normal bank when continuous read commands are occurred to the selected normal bank.

Abstract: A delay locked loop includes a variable delay unit, a phase inversion unit, a delay selecting unit, a delay control unit and an inversion control unit. The variable delay unit delays a reference clock signal based on phase difference between a first feedback clock signal and a reference clock signal, outputted from the delay control unit. The phase inversion unit selectively inverts the delayed clock signal in response to a phase inversion control signal and generates a reproduction clock signal. The delay selecting unit selectively delays the first feedback clock signal corresponding to the reproduction clock signal in response to an inversion control termination signal to generate a second feedback clock signal. The inversion control unit generates the phase inversion control signal when the phase difference between the delayed feedback clock signal and the reference clock signal is larger than a half clock-cycle, and generates the inversion control termination signal.

Abstract: A high voltage generating circuit is disclosed. In the high voltage generating circuit a boost node is precharged and boosted by a plurality of pump circuits and then discharged to an output terminal. Where a voltage apparent at the boost node is smaller than a power supply voltage, the voltage apparent at the boost node is elevated to the power supply voltage. Where the voltage apparent at the boost node is larger than the power supply voltage, a current path is prevented from forming between the boost node and the power supply voltage so as to maintain the voltage apparent at the boost node.

Abstract: A duty cycle correction (DCC) circuit including first and second clock dividers for dividing ordinary and sub-input clocks. Optional first and second variable delay devices delay the divided clocks. First and second mixers mix an optionally delayed ordinary divided clock and sub-ordinary divided clock, or an ordinary divided clock and an optionally delayed sub-ordinary divided clock. A logic combination device is included to produce a clock at the same frequency as the ordinary and sub-input clocks, with a corrected duty cycle.

Abstract: A semiconductor memory device configured to share a local I/O line is described herein. The device includes: a memory cell array including a plurality of memory cells; a plurality of bit line sense amplifiers configured to sense and to amplify data stored in the plurality of memory cells; a plurality of bit lines configured to transmit transmitting the data stored in the plurality of memory cells to the plurality of bit line sense amplifiers, respectively; a plurality of bit line dividing circuits configured to selectively divide the plurality of bit lines; and a plurality of column selecting circuits configured to sequentially transmit the data amplified by the plurality of bit line sense amplifiers to corresponding I/O lines.

Abstract: The present invention provides a duty cycle correction circuit (DCC) and a delay locked loop (DLL) including the same. The inventive duty cycle correction circuit includes: a first clock dividing unit and a second clock dividing unit for dividing an ordinary input clock and a sub ordinary input clock; a first clock mixing unit; a second clock mixing unit; and a logic combination unit for generating a duty cycle correction clock. In addition, the inventive delay locked loop (DLL) includes: a first and second clock dividing unit; a frequency detecting unit; a first variable delaying unit; a second variable delaying unit; a first clock mixing unit; a second clock mixing unit; and a logic combination unit.

Abstract: A DRAM with a general interleaving scheme for data input/output uses a normal bank structure. The DRAM provides a high-performance without consideration of a data access pattern. In order to implement the high-performance, the DRAM includes a plurality of normal banks, at least one cache bank, which has the same data access scheme with the normal banks, for selectively storing data with a normal bank selected at a read mode and a controller for controlling the access to the cache bank and the selected normal bank when continuous read commands are occurred to the selected normal bank.

Abstract: A semiconductor memory device configured to share a local I/O line is described herein. The device includes: a memory cell array including a plurality of memory cells; a plurality of bit line sense amplifiers configured to sense and to amplify data stored in the plurality of memory cells; a plurality of bit lines configured to transmit transmitting the data stored in the plurality of memory cells to the plurality of bit line sense amplifiers, respectively; a plurality of bit line dividing circuits configured to selectively divide the plurality of bit lines; and a plurality of column selecting circuits configured to sequentially transmit the data amplified by the plurality of bit line sense amplifiers to corresponding I/O lines.

Abstract: A method of storing information in a memory cell. The method writes information via only the bit-line that is connected to a memory cell with respect to a word-line, and thus reduces the overall power consumption in the memory by reducing the unnecessary power consumption occurring from the change of voltage level in the bit-line that is not connected to a memory cell. To this end, a method of storing information in a memory cell having a sense amplifier which differentially amplifies a difference in voltage level between a pair of bit-lines is provided, the method comprising the steps of activating a word-line connected to the memory cell to be accessed, differentially amplifying the difference in voltage level between the pair of bit-lines coupled to the memory cell to be accessed, and selecting only one bit-line that is connected to the memory cell among the pair of bit-lines and rewriting the information via the one bit-line.