Abstract: A modified conjugated diene-based polymer having high linearity and improved compounding properties is provided. The modified conjugated diene-based polymer includes phosphor, sulfur and chlorine in specific amount ranges, and the degree of branching is controlled, and accordingly, if applied to a rubber composition, tensile strength and viscoelasticity may be excellent, and processability may be markedly improved.

Abstract: A Rambus ASIC having a high speed testing function and a testing method thereof are disclosed, in which a high speed test of 500MHz or greater is realized using a low frequency testing system. The Rambus ASIC having a high speed testing function includes a Rambus ASIC chip constituting a master device, which includes an RAC with a first data input/output speed, a Rambus DRAM constituting a slave device, a test comparator for driving or comparing data at a second speed lower than the first data input/output speed through each I/O pin in the Rambus ASIC chip, an operating clock supply part for supplying an operating clock to the RAC of the Rambus ASIC chip by varying the operating clock in data writing and reading under the control of the frequency of the test comparator, and a test logic part for outputting data input/output test signals to the test comparator by temporarily storing and comparing data writing/reading signals in the Rambus DRAM.

Abstract: An input/output device in an integrated circuit including a plurality of input buffer units for buffering a data signal provided through each input pin or a test data signal to output it to a core logic, and outputting an inverted test data signal, according to a first test signal; a plurality of output buffer units for selecting and buffering the data signal provided from the core logic or the test data signal, providing the buffered data to each output pin, and outputting an inverted test data signal, according to the first test signal; and a plurality of input/output buffer units for buffering the data signal provided from the core logic or the test data signal to output it to each input/output pin and output an inverted test data signal, and buffering the data signal inputted through each input/output pin to output it to the core logic.

Abstract: A conversion characteristic test circuit and method for an A/D converter uses a DNL error, an INL error, and a dynamic conversion characteristic to analyze digital data output from an A/D converter for judging an operation state of the A/D converter. The conversion characteristic test circuit includes a data detecting unit that detects a digital code randomly output from the A/D converter. A test signal generating unit generates a sequential test signal in accordance with a test clock signal. A DNL error data detecting unit receives a data output by the data detecting unit in accordance with the sequential test signal and subtracts the data from an code-by ideal data to compute DNL error data. An INL error data detecting unit computes INL error data based on the DNL error data and the test clock signal. A judging unit receives the outputs of the DNL error data detecting unit and the INL error data detecting unit and detects a DNL error and an INL error to judge an operation state of the A/D converter.

Abstract: A method and apparatus are provided for testing whether an electronic circuit, or DUT, for generating a clock signal is generating a signal of a frequency within a regulated frequency range. The method includes the steps of: supplying a driving clock or signal to cause the circuit to be tested to generate test clock signals as designed; causing a clock generator to generate an upper limit frequency clock signal and a lower limit frequency clock signal based on the clock signal of the circuit; simultaneously counting the testing clock signal of the circuit, the upper limit frequency clock signal and the lower limit frequency clock signal of the clock generator, and generating resultant signals upon the count reaching certain numbers; and issuing a pass signal when a count result of the upper limit frequency clock signals is output first, and a count result of the testing clock signal of the circuit is output next, and otherwise issuing a fail signal.