Abstract: An image sensing device includes: a control circuit coupled between an output terminal of a pixel signal and a high voltage terminal, and configured to generate a control voltage corresponding to a voltage level of the pixel signal; and a current supplying circuit coupled between the output terminal and the high voltage terminal, and configured to supply a pre-charge current, which is configured to be adaptively adjusted according to the voltage level of the pixel signal, to the output terminal based on the control voltage.

Abstract: Provided is a method for electrowinning neodymium compound. The method includes providing a fluoride-based electrolyte through an opening defined in an electrolytic bath including a cathode and an anode. The method includes providing granules, each including a neodymium compound and having at least one cavity defined therein, through the opening defined in the electrolytic bath. The method includes dissolving at least a portion of the granule in a molten salt of the fluoride-based electrolyte. The method also includes reducing neodymium at the cathode. The cavity is defined inside or on the surface of the granule, and the apparent density of the granules is lower than the density of the molten salt. The method proposed has an improved process compared to those of the related art.

Abstract: An electronic device may include a semiconductor memory structured to include a plurality of memory cells, wherein each of the plurality of memory cells may comprise: a first electrode layer; a second electrode layer; and a selection element layer disposed between the first electrode layer and the second electrode layer to electrically couple or decouple an electrical connection between the first electrode layer and the second electrode layer based on a magnitude of an applied voltage or an applied current with respect to a threshold magnitude, wherein the selection element layer has a dopant concentration profile which decreases from an interface between the selection element layer and the first electrode layer toward an interface between the selection element layer and the second electrode layer.

Abstract: A semiconductor device may include: a plurality of first conductive lines extending in a first direction; a plurality of second conductive lines extending in a second direction; a plurality of memory cells respectively disposed at intersection regions between the first conductive lines and the second conductive lines; and a layer formed between each memory cell and at least one of a first conductive line and an intersecting second conductive line between which the memory cell is located, wherein the layer includes a conductive material that is capable of generating a void to create an open circuit by electromigration when a current applied to the layer through the first conductive line and the second conductive line exceeds a threshold current and is electrically conductive when the current applied to the layer through the first conductive line and the second conductive line is below the threshold current.

Abstract: A semiconductor device may include: a plurality of first conductive lines extending in a first direction; a plurality of second conductive lines spaced apart from the first conductive lines and extending in a second direction intersecting the first direction; and a plurality of memory cells respectively disposed to overlap intersection regions of the plurality of the first conductive lines and the plurality of the second conductive lines; and a layer structured to include an insulating material containing metal ions and formed between each memory cell and at least one of a first conductive line and a second conductive line that intersects with each other at a memory cell.

Abstract: Disclosed are a method of operating a selector device, a method of operating a nonvolatile memory apparatus to which the selector device is applied, an electronic circuit device including the selector device, and a nonvolatile memory apparatus. The method of operating the selector device controls access to a memory element, and includes providing the selector device including a switching layer and first and second electrodes disposed on both surfaces of the switching layer, which includes an insulator and a metal element, and applying a multi-step voltage pulse to the switching layer via the first and second electrodes to adjust a threshold voltage of the selector device, the multi-step voltage pulse including a threshold voltage control pulse and an operating voltage pulse. The operating voltage pulse has a magnitude for turning on the selector device, and the threshold voltage control pulse has a lower magnitude lower than the operating voltage pulse.

Abstract: Operating a selector device that controls access of a signal to a memory element may comprise applying a main operating voltage pulse and a refresh voltage pulse to the selector device. The refresh voltage pulse and main operating voltage pulse have opposite polarities. A magnitude of the main operating voltage pulse is greater than or equal to a threshold voltage for turning on the selector device, and a maximum magnitude of the refresh voltage pulse is less than the threshold voltage. The refresh voltage pulse reduces a difference between the threshold voltage and a turn-off voltage of the selector device, and may be applied immediately before or immediately after the main operating voltage pulse. An electronic circuit may include the selector device and a driving circuit for apply the pulses. A nonvolatile memory may include the driving circuit and a plurality of nonvolatile memory elements each including a selector device.

Abstract: An electronic device may include a semiconductor memory structured to include a plurality of memory cells, wherein each of the plurality of memory cells may comprise: a first electrode layer; a second electrode layer; and a selection element layer disposed between the first electrode layer and the second electrode layer to electrically couple or decouple an electrical connection between the first electrode layer and the second electrode layer based on a magnitude of an applied voltage or an applied current with respect to a threshold magnitude, wherein the selection element layer has a dopant concentration profile which decreases from an interface between the selection element layer and the first electrode layer toward an interface between the selection element layer and the second electrode layer.

Abstract: Disclosed is a nonvolatile memory device including a plurality of memory cells operable to store data, each memory cell structured to include a resistance change layer exhibiting different resistance states with different resistance values for representing data, a write circuit suitable for generating a write pulse in a write mode to write data in a memory cell of the plurality of memory cells, and a read circuit suitable for generating a read pulse in a read mode to read data from a memory cell of the plurality of memory cells, wherein the memory cells are each structured to be operable in writing or reading data when a range of a voltage level change of the read pulse corresponding to a pulse width change of the read pulse is within a range of a voltage level change of the write pulse corresponding to a pulse width change of the write pulse.

Abstract: An electronic device may include a semiconductor memory structured to include a plurality of memory cells, wherein each of the plurality of memory cells may comprise: a first electrode layer; a second electrode layer; and a selection element layer disposed between the first electrode layer and the second electrode layer to electrically couple or decouple an electrical connection between the first electrode layer and the second electrode layer based on a magnitude of an applied voltage or an applied current with respect to a threshold magnitude, wherein the selection element layer has a dopant concentration profile which decreases from an interface between the selection element layer and the first electrode layer toward an interface between the selection element layer and the second electrode layer.

Abstract: A semiconductor memory may include: a first variable resistance element including a first terminal and a second terminal; a second variable resistance element including a first terminal, a second terminal, and a third terminal; a first transistor configured to control an electrical connection between a first conductive line and the first terminal of the first variable resistance element; a second transistor configured to control an electrical connection between the first conductive line and the first terminal of the second variable resistance element; a connection layer structured to electrically connect the second terminal of the first variable resistance element to the second and third terminals of the second variable resistance element; and a third conductive line is electrically connected to the connection layer.

Abstract: A semiconductor memory may include at least one memory cell. The memory cell may include: a first electrode layer; a second electrode layer separated from the first electrode layer, wherein the first and second electrode layers are coupled to receive a voltage applied to the first and second electrode layers; and a self-selecting memory layer interposed between the first electrode layer and the second electrode layer and configured to store data and operable to disconnect or connect a conducting path between the first electrode layer and the second electrode layer, to respond to the voltage applied to the first and second electrode layers, wherein the self-selecting memory layer includes an insulating material layer, a first dopant that creates a shallow trap providing a path for conductive carriers in the insulating material layer, and a second dopant that is movable in the insulating material layer according to a polarity of the voltage applied to the first and second electrode layers.

Abstract: A semiconductor device may include at least one memory cell. The memory cell may include: a first electrode layer; a second electrode layer; and a self-selecting memory layer interposed between the first electrode layer and the second electrode layer and exhibits different resistance states for storing data and is structured to be either electrically conductive or electrically non-conductive in response to a voltage applied to the first and second electrode layers, wherein the self-selecting memory layer includes a ferroelectric layer exhibiting deep traps for trapping conductive carriers and a first dopant doped in the ferroelectric layer to form shallow traps providing a conductive path for conductive carriers to move in the ferroelectric layer.

Abstract: A semiconductor device may include: a first conductive line; a second conductive line disposed over the first conductive line to be spaced apart from the first conductive line; a variable resistance layer disposed over the first conductive line and below the second conductive line; at least one of a first dielectric layer or a second dielectric layer; at least one of a first contact or a second contact; and at least one of a first doped selector layer or a second doped selector layer.

Abstract: A semiconductor device including at least one memory cell is provided. The memory cell includes: a first electrode layer; a second electrode layer; a selection element layer coupled between the first electrode layer and the second electrode layer; and an insulating layer coupled between the first electrode layer and the second electrode such that a side surface of the insulating layer is in contact with a side surface of the selection element layer, wherein the selection element layer includes an insulating material doped with a first element, and wherein the insulating layer includes the insulating material doped with the first element at a lower concentration than the selection element layer, or the insulating material not doped with the first element.

Abstract: Disclosed are a method of operating a selector device, a method of operating a nonvolatile memory apparatus to which the selector device is applied, an electronic circuit device including the selector device, and a nonvolatile memory apparatus. The method of operating the selector device controls access to a memory element, and includes providing the selector device including a switching layer and first and second electrodes disposed on both surfaces of the switching layer, which includes an insulator and a metal element, and applying a multi-step voltage pulse to the switching layer via the first and second electrodes to adjust a threshold voltage of the selector device, the multi-step voltage pulse including a threshold voltage control pulse and an operating voltage pulse. The operating voltage pulse has a magnitude for turning on the selector device, and the threshold voltage control pulse has a lower magnitude lower than the operating voltage pulse.

Abstract: An electronic device may include a semiconductor memory structured to include a plurality of memory cells, wherein each of the plurality of memory cells may comprise: a first electrode layer; a second electrode layer; and a selection element layer disposed between the first electrode layer and the second electrode layer to electrically couple or decouple an electrical connection between the first electrode layer and the second electrode layer based on a magnitude of an applied voltage or an applied current with respect to a threshold magnitude, wherein the selection element layer has a dopant concentration profile which decreases from an interface between the selection element layer and the first electrode layer toward an interface between the selection element layer and the second electrode layer.

Abstract: According to embodiments of the present invention, an alignment method for a silicon photonics packaging is provided. The method includes providing a plurality of waveguides, each of the plurality of waveguides including an input and an output, arranging a light source relative to the plurality of waveguides, the light source being configured to provide an input light to the input of at least one of the plurality of waveguides, detecting respective output light intensity exiting the outputs of the plurality of waveguides, and identifying based on the detected output light intensity a selected waveguide of the plurality of waveguides for subsequent coupling.

Abstract: An optical module having a second connector unit mounted on the bottom of a first connector unit to reduce the size of the radiation member and the optical module. The optical module includes a first connector unit, a radiation member provided on a first side of the first connector unit to support the first connector unit and radiate heat, a second connector provided on the first connector unit to electrically connect the first connector unit to a PCB, and a fastening member provided on surfaces of the first and second connector units, which face each other, to fasten the first and second connectors to each other. The optical module is advantageous reduces the size of the radiation member and renders a more compact optical module.

Abstract: An optical module having a second connector unit mounted on the bottom of a first connector unit to reduce the size of the radiation member and the optical module. The optical module includes a first connector unit, a radiation member provided on a first side of the first connector unit to support the first connector unit and radiate heat, a second connector provided on the first connector unit to electrically connect the first connector unit to a PCB, and a fastening member provided on surfaces of the first and second connector units, which face each other, to fasten the first and second connectors to each other. The optical module is advantageous reduces the size of the radiation member and renders a more compact optical module.