Patents by Inventor Jeong-Hwan Yang

Jeong-Hwan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240381764
    Abstract: The present disclosure relates to a plurality of host materials, an organic electroluminescent compound, and an organic electroluminescent device comprising the same. An organic electroluminescent device with improved driving voltage, luminous efficiency and/or lifespan properties can be provided by comprising the specific combination of compounds according to the present disclosure as a host material, or by comprising compounds according to the present disclosure.
    Type: Application
    Filed: March 4, 2024
    Publication date: November 14, 2024
    Inventors: Jeong-Eun YANG, Ga-Won LEE, Hee-Ryong KANG, Hyo-Soon PARK, Sang-Hee CHO, Jeong-Hwan JEON
  • Publication number: 20240371752
    Abstract: A semiconductor device may include: a first gate structure including a plurality of first conductive layers that are alternately stacked with a plurality of first insulating layers; a second gate structure including a plurality of second conductive layers that are alternately stacked with a plurality of second insulating layers; a third gate structure including third conductive layers that are alternately stacked with a plurality of third insulating layers; and a first contact plug extending into the first gate structure through the third gate structure and the second gate structure, the first contact plug connected to a first of the plurality of first conductive layers, and the first contact plug including a first inflection portion located at an interface between the second gate structure and the third gate structure.
    Type: Application
    Filed: April 8, 2024
    Publication date: November 7, 2024
    Applicant: SK hynix Inc.
    Inventors: Won Geun CHOI, Jung Shik JANG, Rho Gyu KWAK, Seok Min CHOI, Jeong Hwan KIM, Na Yeong YANG, In Su PARK, Jung Dal CHOI
  • Patent number: 12137611
    Abstract: The present disclosure provides a compound of following formula and an organic light emitting device and an organic light emitting display device including the compound. The compound of the present disclosure serves as a host or a dopant in an emitting material layer.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: November 5, 2024
    Assignee: LG Display Co., Ltd.
    Inventors: Kyung-Jin Yoon, Yu-Jin Bae, Bo-Min Seo, Jeong-Eun Baek, Joong-Hwan Yang, Chun-Ki Kim, Jung-Hyun Yoon, Hyung-Won Cho, Kyu-Soon Shin, Jeong-A Seo, Hyung-Jin Lee, Young-Sam Jin, Dong-Hyun Lee
  • Patent number: 12038593
    Abstract: Provided is a near-infrared ray absorbing article. A near-infrared ray absorbing article of the present invention is capable of preventing a decrease in visible transmittance and near-infrared absorption due to the interaction between a plurality of organic materials forming light-absorbing layers. In addition, the near-infrared ray absorbing article of the present invention has the advantage of being able to be thinner. In addition, the near-infrared ray absorbing article of the present invention has the advantage of excellent mechanical properties such as strength and heat resistance.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: July 16, 2024
    Assignee: LMS CO., LTD.
    Inventors: Sung Hwan Moon, Seon Ho Yang, Choon Woo Ji, Nam Woo Kang, Joon Ho Jung, Bo Chul Kang, Hee Kyeong Kim, Jeong Og Choi, Seong Yong Yoon
  • Patent number: 10680447
    Abstract: Provided are a charge equalization apparatus for a battery string. According to the exemplary embodiments of the present invention, the charge equalization apparatus are modularized by being divided into the master unit and the slave unit, such that the charge equalization apparatus may be expanded and contracted independent of the number of batteries, the circuits are separated for each module, such that the circuits may be easily implemented, and when the circuits are damaged, only the damaged module is replaced, such that the effective countermeasure may be performed.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: June 9, 2020
    Assignee: SK INNOVATION CO., LTD.
    Inventors: Jeong Hwan Yang, Gun-Woo Moon, Chol-Ho Kim, Moon-Young Kim
  • Patent number: 10274584
    Abstract: The present invention relates to an apparatus and method for generating a bidirectional chirp signal by using a phase accumulation polynomial, and the apparatus for generating a bidirectional chirp signal according to an embodiment may include an extraction unit extracting time interval information from the output of a frequency accumulator, a polynomial handling unit applying the phase accumulation polynomial to the extracted time interval information to generate a polynomial output value, and a bidirectional chirp signal output unit outputting a bidirectional chirp signal on the basis of the generated polynomial output value.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: April 30, 2019
    Assignee: KOREA AEROSPACE RESEARCH INSTITUTE
    Inventors: Sang Burm Ryu, Jeong Hwan Yang, Jong Pyo Kim, Young Jin Won, Young Jun Cho, Chul Kang, Sang Kon Lee
  • Patent number: 9899386
    Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: February 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Jeong Hwan Yang
  • Publication number: 20170288422
    Abstract: Provided are a charge equalization apparatus for a battery string. According to the exemplary embodiments of the present invention, the charge equalization apparatus are modularized by being divided into the master unit and the slave unit, such that the charge equalization apparatus may be expanded and contracted independent of the number of batteries, the circuits are separated for each module, such that the circuits may be easily implemented, and when the circuits are damaged, only the damaged module is replaced, such that the effective countermeasure may be performed.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 5, 2017
    Inventors: Jeong Hwan YANG, Gun-Woo MOON, Chol-Ho KIM, Moon-Young KIM
  • Publication number: 20160379980
    Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.
    Type: Application
    Filed: July 15, 2016
    Publication date: December 29, 2016
    Inventors: Shigenobu Maeda, Jeong Hwan Yang
  • Publication number: 20160370457
    Abstract: The present invention relates to an apparatus and method for generating a bidirectional chirp signal by using a phase accumulation polynomial, and the apparatus for generating a bidirectional chirp signal according to an embodiment may include an extraction unit extracting time interval information from the output of a frequency accumulator, a polynomial handling unit applying the phase accumulation polynomial to the extracted time interval information to generate a polynomial output value, and a bidirectional chirp signal output unit outputting a bidirectional chirp signal on the basis of the generated polynomial output value.
    Type: Application
    Filed: November 20, 2014
    Publication date: December 22, 2016
    Applicant: KOREA AEROSPACE RESEARCH INSTITUTE
    Inventors: Sang Burm Ryu, Jeong Hwan Yang, Jong Pyo Kim, Young Jin Won, Young Jun Cho, Chul Kang, Sang Kon Lee
  • Patent number: 9425182
    Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: August 23, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Jeong Hwan Yang
  • Publication number: 20150311189
    Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.
    Type: Application
    Filed: July 6, 2015
    Publication date: October 29, 2015
    Inventors: Shigenobu Maeda, Jeong-Hwan Yang
  • Patent number: 9123811
    Abstract: In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: September 1, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shigenobu Maeda, Jeong Hwan Yang, Junga Choi
  • Patent number: 9093306
    Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: July 28, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Jeong Hwan Yang
  • Patent number: 9069024
    Abstract: An insulation resistance measurement circuit in which switching of first and second switches is controlled such that a leakage current may not be generated in measuring insulation resistance, and voltages output through first and second operational amplifiers are measured after opening the first and second switches and closing third and fourth switches for self-testing of the insulation resistance measurement circuit.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: June 30, 2015
    Assignee: SK INNOVATION CO., LTD.
    Inventor: Jeong Hwan Yang
  • Patent number: 9018905
    Abstract: The present invention relates to a battery management apparatus of a high voltage battery for a hybrid vehicle, in more detail, a battery management apparatus of a high voltage battery for a hybrid vehicle which includes: a plurality of battery packs including a plurality of unit cells; slave battery management modules measuring and monitoring temperature and voltage of the unit cells in the battery packs; temperature/voltage measurement wires connecting the unit cells with adjacent unit cells for the slave battery management modules to measure temperature and voltage between the unit cells and the adjacent unit cells; a master battery management module connected with the slave battery management modules; and communication wires connecting the modules.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: April 28, 2015
    Assignee: SK Innovation Co., Ltd.
    Inventors: Jae Hwan Lim, Jeong Hwan Yang, Soo Yeup Jang
  • Publication number: 20140332897
    Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.
    Type: Application
    Filed: July 22, 2014
    Publication date: November 13, 2014
    Inventors: Shigenobu Maeda, Jeong Hwan Yang
  • Patent number: 8866438
    Abstract: Provided are a system and a method for providing reactive power using an electric car battery, and more particularly, a system and a method for providing reactive power to a micro-grid using a bidirectional charger that is an electric car battery and an electric car charging device.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: October 21, 2014
    Assignee: SK Innovation Co., Ltd.
    Inventors: Kil Su Lee, Jeong Hwan Yang, Sang Hyun Park
  • Patent number: 8816440
    Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Jeong Hwan Yang
  • Patent number: 8779784
    Abstract: Provided is an insulation resistance measuring circuit including: a source resistor unit including a first source resistor connected between a positive terminal of a battery and a second source resistor and the second source resistor connected between a negative terminal of the battery and the first source resistor; a voltage sensing unit sensing a voltage of the first source resistor as a first voltage and sensing a voltage of the second source resistor as a second voltage; and an insulation resistance measuring unit measuring an insulation resistance of the battery through a value obtained by dividing a difference between the first and second voltages by a sum between the first and second voltages.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: July 15, 2014
    Assignee: SK Innovation Co., Ltd.
    Inventors: Jeong Hwan Yang, Ki Seok Choi, Jae Hwan Lim