Patents by Inventor Jeong-Hwan Yang
Jeong-Hwan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250107078Abstract: A semiconductor device may include a gate structure including stacked local lines and a multi-step structure, wherein the multi-step structure defines pads of the local lines, channel patterns respectively disposed over the pads, a block word line disposed over the channel patterns and extending along a profile of the multi-step structure, and first contact plugs passing through the channel patterns and respectively connecting the channel patterns and the local lines.Type: ApplicationFiled: December 21, 2023Publication date: March 27, 2025Inventors: Seok Min CHOI, Jeong Hwan KIM, Jung Shik JANG, Rho Gyu KWAK, In Su PARK, Na Yeong YANG, Won Geun CHOI, Jung Dal CHOI
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Patent number: 12257034Abstract: An apparatus for estimating bio-information is disclosed. The apparatus may include: a pulse wave sensor configured to measure a pulse wave signal from an object; a force sensor configured to obtain a force signal by measuring an external force exerted onto the force sensor; and a processor configured to obtain a first input value, a second input value, and a third input value based on the pulse wave signal and the force signal, to extract a feature vector by inputting the first input value, the second input value, and the third input value into a first neural network model, and to obtain the bio-information by inputting the feature vector into a second neural network model.Type: GrantFiled: July 7, 2021Date of Patent: March 25, 2025Assignees: SAMSUNG ELECTRONICS CO., LTD., IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)Inventors: Sang Kon Bae, Joon-Hyuk Chang, Jin Woo Choi, Youn Ho Kim, Jehyun Kyung, Joon-Young Yang, Inmo Yeon, Jeong-Hwan Choi
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Patent number: 10680447Abstract: Provided are a charge equalization apparatus for a battery string. According to the exemplary embodiments of the present invention, the charge equalization apparatus are modularized by being divided into the master unit and the slave unit, such that the charge equalization apparatus may be expanded and contracted independent of the number of batteries, the circuits are separated for each module, such that the circuits may be easily implemented, and when the circuits are damaged, only the damaged module is replaced, such that the effective countermeasure may be performed.Type: GrantFiled: April 24, 2017Date of Patent: June 9, 2020Assignee: SK INNOVATION CO., LTD.Inventors: Jeong Hwan Yang, Gun-Woo Moon, Chol-Ho Kim, Moon-Young Kim
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Patent number: 10274584Abstract: The present invention relates to an apparatus and method for generating a bidirectional chirp signal by using a phase accumulation polynomial, and the apparatus for generating a bidirectional chirp signal according to an embodiment may include an extraction unit extracting time interval information from the output of a frequency accumulator, a polynomial handling unit applying the phase accumulation polynomial to the extracted time interval information to generate a polynomial output value, and a bidirectional chirp signal output unit outputting a bidirectional chirp signal on the basis of the generated polynomial output value.Type: GrantFiled: November 20, 2014Date of Patent: April 30, 2019Assignee: KOREA AEROSPACE RESEARCH INSTITUTEInventors: Sang Burm Ryu, Jeong Hwan Yang, Jong Pyo Kim, Young Jin Won, Young Jun Cho, Chul Kang, Sang Kon Lee
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Patent number: 9899386Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.Type: GrantFiled: July 15, 2016Date of Patent: February 20, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Shigenobu Maeda, Jeong Hwan Yang
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Publication number: 20170288422Abstract: Provided are a charge equalization apparatus for a battery string. According to the exemplary embodiments of the present invention, the charge equalization apparatus are modularized by being divided into the master unit and the slave unit, such that the charge equalization apparatus may be expanded and contracted independent of the number of batteries, the circuits are separated for each module, such that the circuits may be easily implemented, and when the circuits are damaged, only the damaged module is replaced, such that the effective countermeasure may be performed.Type: ApplicationFiled: April 24, 2017Publication date: October 5, 2017Inventors: Jeong Hwan YANG, Gun-Woo MOON, Chol-Ho KIM, Moon-Young KIM
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Publication number: 20160379980Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.Type: ApplicationFiled: July 15, 2016Publication date: December 29, 2016Inventors: Shigenobu Maeda, Jeong Hwan Yang
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Publication number: 20160370457Abstract: The present invention relates to an apparatus and method for generating a bidirectional chirp signal by using a phase accumulation polynomial, and the apparatus for generating a bidirectional chirp signal according to an embodiment may include an extraction unit extracting time interval information from the output of a frequency accumulator, a polynomial handling unit applying the phase accumulation polynomial to the extracted time interval information to generate a polynomial output value, and a bidirectional chirp signal output unit outputting a bidirectional chirp signal on the basis of the generated polynomial output value.Type: ApplicationFiled: November 20, 2014Publication date: December 22, 2016Applicant: KOREA AEROSPACE RESEARCH INSTITUTEInventors: Sang Burm Ryu, Jeong Hwan Yang, Jong Pyo Kim, Young Jin Won, Young Jun Cho, Chul Kang, Sang Kon Lee
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Patent number: 9425182Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.Type: GrantFiled: July 6, 2015Date of Patent: August 23, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Shigenobu Maeda, Jeong Hwan Yang
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Publication number: 20150311189Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.Type: ApplicationFiled: July 6, 2015Publication date: October 29, 2015Inventors: Shigenobu Maeda, Jeong-Hwan Yang
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Patent number: 9123811Abstract: In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.Type: GrantFiled: March 12, 2012Date of Patent: September 1, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shigenobu Maeda, Jeong Hwan Yang, Junga Choi
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Patent number: 9093306Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.Type: GrantFiled: July 22, 2014Date of Patent: July 28, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Shigenobu Maeda, Jeong Hwan Yang
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Patent number: 9069024Abstract: An insulation resistance measurement circuit in which switching of first and second switches is controlled such that a leakage current may not be generated in measuring insulation resistance, and voltages output through first and second operational amplifiers are measured after opening the first and second switches and closing third and fourth switches for self-testing of the insulation resistance measurement circuit.Type: GrantFiled: September 16, 2011Date of Patent: June 30, 2015Assignee: SK INNOVATION CO., LTD.Inventor: Jeong Hwan Yang
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Patent number: 9018905Abstract: The present invention relates to a battery management apparatus of a high voltage battery for a hybrid vehicle, in more detail, a battery management apparatus of a high voltage battery for a hybrid vehicle which includes: a plurality of battery packs including a plurality of unit cells; slave battery management modules measuring and monitoring temperature and voltage of the unit cells in the battery packs; temperature/voltage measurement wires connecting the unit cells with adjacent unit cells for the slave battery management modules to measure temperature and voltage between the unit cells and the adjacent unit cells; a master battery management module connected with the slave battery management modules; and communication wires connecting the modules.Type: GrantFiled: November 9, 2010Date of Patent: April 28, 2015Assignee: SK Innovation Co., Ltd.Inventors: Jae Hwan Lim, Jeong Hwan Yang, Soo Yeup Jang
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Publication number: 20140332897Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.Type: ApplicationFiled: July 22, 2014Publication date: November 13, 2014Inventors: Shigenobu Maeda, Jeong Hwan Yang
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Patent number: 8866438Abstract: Provided are a system and a method for providing reactive power using an electric car battery, and more particularly, a system and a method for providing reactive power to a micro-grid using a bidirectional charger that is an electric car battery and an electric car charging device.Type: GrantFiled: December 2, 2011Date of Patent: October 21, 2014Assignee: SK Innovation Co., Ltd.Inventors: Kil Su Lee, Jeong Hwan Yang, Sang Hyun Park
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Patent number: 8816440Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.Type: GrantFiled: January 4, 2011Date of Patent: August 26, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Shigenobu Maeda, Jeong Hwan Yang
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Patent number: 8779784Abstract: Provided is an insulation resistance measuring circuit including: a source resistor unit including a first source resistor connected between a positive terminal of a battery and a second source resistor and the second source resistor connected between a negative terminal of the battery and the first source resistor; a voltage sensing unit sensing a voltage of the first source resistor as a first voltage and sensing a voltage of the second source resistor as a second voltage; and an insulation resistance measuring unit measuring an insulation resistance of the battery through a value obtained by dividing a difference between the first and second voltages by a sum between the first and second voltages.Type: GrantFiled: March 23, 2010Date of Patent: July 15, 2014Assignee: SK Innovation Co., Ltd.Inventors: Jeong Hwan Yang, Ki Seok Choi, Jae Hwan Lim
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Publication number: 20140117414Abstract: In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.Type: ApplicationFiled: January 8, 2014Publication date: May 1, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Shigenobu Maeda, Jeong Hwan Yang, Junga Choi
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Patent number: 8710555Abstract: In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.Type: GrantFiled: March 12, 2012Date of Patent: April 29, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Shigenobu Maeda, Jeong Hwan Yang, Junga Choi