Abstract: The present invention relates to a connector which is a component of a high-voltage power supply connecting device, and which is capable of being prevented from being easily separated inadvertently or by an inexpert operator to prevent the occurrence of an electric shock accident, is capable of preventing the occurrence of an electric arc or the like during separation of the connector to improve safety, is capable of being easily and stably fixed and mounted on a desired location in an installation path inside an electric equipment chamber of an electric car, has a simple structure, and is capable of improving workability of an operator; and the high-voltage power supply connecting device including the same.

Abstract: The present invention relates to a connector which is a component of a high-voltage power supply connecting device, and which is capable of being prevented from being easily separated inadvertently or by an inexpert operator to prevent the occurrence of an electric shock accident, is capable of preventing the occurrence of an electric arc or the like during separation of the connector to improve safety, is capable of being easily and stably fixed and mounted on a desired location in an installation path inside an electric equipment chamber of an electric car, has a simple structure, and is capable of improving workability of an operator; and the high-voltage power supply connecting device including the same.

Abstract: Disclosed is a high-voltage male connector including: a male terminal formed of a metal material and having a plate shape; an insulating cap provided on a front end of the male terminal; an inner housing into which the male terminal is inserted and mounted such that the front end of the male terminal faces the outside; a partition unit integrally formed with an inner side of the inner housing and having a tetragonal pipe shape covering the male terminal; and an outer housing which is formed of a metal material and into which the inner housing is inserted and mounted.

Abstract: Disclosed is a high-voltage male connector including: a male terminal formed of a metal material and having a plate shape; an insulating cap provided on a front end of the male terminal; an inner housing into which the male terminal is inserted and mounted such that the front end of the male terminal faces the outside; a partition unit integrally formed with an inner side of the inner housing and having a tetragonal pipe shape covering the male terminal; and an outer housing which is formed of a metal material and into which the inner housing is inserted and mounted.

Abstract: In a non-volatile semiconductor memory device having a storage cell array and a peripheral circuit, the thickness of a gate oxide layer of the peripheral circuit area is independent of the formation of an O--N--O insulation layer on the storage cell area. A floating gate of a storage cell array is formed as a first conductive layer on a semiconductor substrate, an O--N--O insulation layer covering the floating gate is formed on the top surface of the substrate, and a gate oxide layer of the peripheral circuit area is formed by making an oxide layer on the top surface of the substrate after removing the O--N--O insulation layer on the top surface of the peripheral circuit area. The O--N--O insulation layer is solely formed on the top and side surfaces of the floating gate in the direction of word lines and absent from side surfaces of the floating gate in the direction of bit lines.

Abstract: A method for fabricating a non-volatile semiconductor memory device having a storage cell array and a peripheral circuit, capable of controlling thickness of gate oxide layer of peripheral circuit area independently of formation of O--N--O insulation layer on storage cell area, is disclosed. A floating gate of a storage cell array is formed as a first conductive layer on a semiconductor substrate, an O--N--O insulation layer enclosing the floating gate is formed on the top surface of the substrate, and a gate oxide layer of peripheral circuit area is formed by making an oxide layer on the top surface of the substrate after removing the O--N--O insulation layer on the top surface of the peripheral circuit area.

Abstract: A method for manufacturing highly integrated NAND and NOR logic mask read only memory (MROM) devices is disclosed. Over the top surface of a semiconductor substrate, where a first polysilicon layer is formed, a pattern of a gate electrode is formed along a word line in the order of odd numbers or even numbers. Next, an insulation layer having a thickness of a submicron range is formed over the top surface of the substrate. And then a photoresist is covered and an etch back process is performed. Thereafter, the exposed insulation layer caused by the etch back process and the polysilicon layer are selectively etched to form a word line spacing corresponding to a thickness of the insulation layer. Thus, spacing between adjacent word lines can be minimized and a process margin can be sufficiently ensured.

Abstract: A nonvolatile semiconductor memory device and the method thereof is disclosed. The nonvolatile semiconductor memory device comprises a first conductive type semiconductor substrate, a field oxide film formed on the semiconductor substrate to define an active region, a source region and a drain region which are separated by a channel region near the surface of semiconductor substrate of the active region and diffused with an impurity of the opposite conductive type to the semiconductor substrate, a thin gate insulating film formed on the channel region and partially on the source and drain regions, a first conductive layer formed on the gate insulating film and provided as a floating electrode for accumulating charges, an interlayer insulating film formed on the first conductive layer, and a second conductive layer formed on the interlayer insulating film and provided as a control electrode.

Abstract: A method for manufacturing highly integrated NAND and NOR logic mask read only memory (MROM) devices is disclosed. Over the top surface of a semiconductor substrate, where a first polysilicon layer is formed, a pattern of a gate electrode is formed along a word line in the order of odd numbers or even numbers. Next, an insulation layer having a thickness of a submicron range is formed over the top surface of the substrate. And then a photoresist is covered and an etch back process is performed. Thereafter, the exposed insulation layer caused by the etch back process and the polysilicon layer are selectively etched to form a word line spacing corresponding to a thickness of the insulation layer. Thus, spacing between adjacent word lines can be minimized and a process margin can be sufficiently ensured.