Patents by Inventor JEONG HYEON PARK
JEONG HYEON PARK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240213590Abstract: Provided is a pouch for a secondary battery and a lithium secondary battery including the same. The pouch for the secondary battery includes a barrier layer, a base material layer disposed on one surface of the barrier layer, and a sealant layer disposed on the other surface of the barrier layer. The sealant layer includes a first sealant layer disposed on directly in contact with the other surface of the barrier layer, and a second sealant layer disposed on the first sealant layer. The sealant layer has a melt flow rate (MFR) of about 14.0 g/10 min or less, which is measured at a temperature of about 230° C. under a load condition of about 2.16 kg.Type: ApplicationFiled: December 19, 2023Publication date: June 27, 2024Applicant: LG Energy Solution, Ltd.Inventors: Min Hyuk Yun, Duck Hoe Kim, In Yong Baek, Ji Young Hwang, Jeong Hyeon Park, Wan Gyeong Jang, Dae Woong Song, Moo Yeon Kim
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Publication number: 20240119211Abstract: A semiconductor design optimization system that includes: a data base configured to store design data, a training data preprocessing unit configured to preprocess the design data and generate training data, a data learning unit configured to generate a physical property prediction model by training using the training data, a physical property prediction unit configured to generate predicted physical property data including information associated with predicted physical property values for each region of a semiconductor device to be fabricated, wherein the physical property prediction unit is configured to input, into the physical property prediction model, input data including information associated with design drawings of the semiconductor device to be fabricated, and a layout generator configured generate a design layout optimized to distribute the predicted physical property values for each region of the semiconductor device to be fabricated by modifying the design drawings based on the predicted physicalType: ApplicationFiled: June 6, 2023Publication date: April 11, 2024Applicants: Samsung Electronics Co., Ltd., Research & Business Foundation SUNGKYUNKWAN UNIVERSITYInventors: Eun-Ho Lee, Jae Choon Kim, Tae-Hyun Kim, Jeong-Hyeon Park, Hwanjoo Park, Sunggu Kang, Sung-Ho Mun
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Publication number: 20230380254Abstract: A method for manufacturing a display device includes providing a donor substrate including a first base substrate and an organic material layer disposed on the first base substrate, etching the organic material layer to form an etched organic material layer using a laser device, providing a display substrate including a second base substrate and a plurality of first electrodes disposed on the second base substrate, aligning the donor substrate and the display substrate such that the etched organic material layer faces the plurality of first electrodes, and transferring the etched organic material layer to the display substrate using an energy generation device.Type: ApplicationFiled: March 28, 2023Publication date: November 23, 2023Applicants: Samsung Display Co., Ltd., Postech Research and Business Development FoundationInventors: Sungsoon IM, Jong Kyu KIM, Hyeon Woong HWANG, Jeong Hyeon PARK, Heemin PARK, Seungyong SONG, Duckjung LEE
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Patent number: 11660068Abstract: A medical headgear includes an ultrasound transducer and a headgear. The ultrasound transducer is configured to generate a low intensity ultrasound. The headgear supports the ultrasound transducer. The headgear includes a rear portion case including a slide guide configured to support an occipital and a support pad configured to support a crown. The headgear further includes a front portion case connected to the rear portion case to be slidably movable in one direction. The front portion case includes two temporal support pads configured to support both temporal portions.Type: GrantFiled: September 11, 2019Date of Patent: May 30, 2023Assignee: NEUROSONA CO., LTD.Inventors: Ji Yeun Kim, Jeong Hyeon Park, Seoung Won Shin, Seung Schik Yoo
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Patent number: 11447859Abstract: Provided are a novel metal triamine compound, a method for preparing the same, a composition for depositing a metal-containing thin film including the same, and a method for preparing a metal-containing thin film using the same. The metal triamine compound of the present invention has excellent reactivity, is thermally stable, has high volatility, and has high storage stability, and thus, it may be used as a metal-containing precursor to easily prepare a high-purity metal-containing thin film having high density.Type: GrantFiled: April 26, 2018Date of Patent: September 20, 2022Assignee: DNF CO., LTD.Inventors: Myong Woon Kim, Sang Ick Lee, Sang Jun Yim, Won Mook Chae, Jeong Hyeon Park, Kang Yong Lee, A Ra Cho, Joong Jin Park, Heang Don Lim
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Publication number: 20210325787Abstract: Provided are an exposure apparatus including a light source unit which provides light for exposure and comprises micro light emitting diodes arranged in a matrix form; a substrate transfer unit which transfers a target substrate; and a control unit which controls at least one of the light source unit and the substrate transfer unit. The control unit allocates coordinates or an address to each micro light emitting diode and individually controls an amount of light of each micro light emitting diode according to a preset pattern based on the coordinates or the address.Type: ApplicationFiled: November 19, 2020Publication date: October 21, 2021Inventors: Sung Soon IM, Jong Kyu KIM, Jeong Hyeon PARK, Seung Yong SONG, Duck Jung LEE, Jong Won LEE
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Publication number: 20210222294Abstract: Provided are a novel metal triamine compound, a method for preparing the same, a composition for depositing a metal-containing thin film including the same, and a method for preparing a metal-containing thin film using the same. The metal triamine compound of the present invention has excellent reactivity, is thermally stable, has high volatility, and has high storage stability, and thus, it may be used as a metal-containing precursor to easily prepare a high-purity metal-containing thin film having high density.Type: ApplicationFiled: April 26, 2018Publication date: July 22, 2021Applicant: DNF Co., Ltd.Inventors: Myong Woon KIM, Sang Ick LEE, Sang Jun YIM, Won Mook CHAE, Jeong Hyeon PARK, Kang Yong LEE, A Ra CHO, Joong Jin PARK, Heang Don LIM
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Publication number: 20210017684Abstract: Disclosure relates to sewing machine capable of preventing thread cutting or deterioration caused by interference between leading end of needle and upper thread, that includes: head frame; needle bar supported on head frame to be movable up and down; needle having needle hole that penetrates in transverse direction with respect to axial line and has upper thread inserted thereinto and be coupled to lower end of needle bar to move up and down between lowered stitching position and lifted needle position; and presser foot unit having pressing part that is provided with needle guide hole through which needle passes and moves up and down between downward pressing height position where pressing part presses sewing material and lifting release height position where pressing part is lifted and spaced apart from sewing material and pressing foot arm that supports pressing part.Type: ApplicationFiled: March 27, 2019Publication date: January 21, 2021Inventor: Jeong Hyeon PARK
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Patent number: 10637467Abstract: A semiconductor device includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first gate insulator, a first source region and a first drain region, a pair of lightly doped drain (LDD) regions that are each shallower than the first source region and the first drain region, and a first gate electrode. The second transistor includes a second gate insulator, a second source region and a second drain region, a pair of drift regions that encompass the second source region and the second drain region respectively, and a second gate electrode, and the third transistor comprises a third gate insulator, a third source region and a third drain region, and a pair of drift regions that encompass the third source and the third drain regions respectively, and a third gate electrode. The second gate insulator is thinner than the other gate insulators.Type: GrantFiled: September 25, 2018Date of Patent: April 28, 2020Assignee: Magnachip Semiconductor, Ltd.Inventors: Jeong Hyeon Park, Bo Seok Oh, Hee Hwan Ji
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Publication number: 20200000428Abstract: Provided are a medical headgear which may be worn on a skull of an object while an ultrasound transducer is supported thereby, and the headgear according to an embodiment of the present disclosure may closely adhere and support an ultrasound transducer to the skull of the object regardless of the size and shape of the skull of the object and a position of the brain to which ultrasound needs to be transmitted. According to the medical headgear as described above, the ultrasound transducer supported on the headgear may be moved to a specific position on the skull, regardless of the position of the brain to which ultrasound needs to be transmitted, and thus, the use convenience of a user may be improved.Type: ApplicationFiled: September 11, 2019Publication date: January 2, 2020Applicant: NEUROSONA CO., LTD.Inventors: Ji Yeun KIM, Jeong Hyeon PARK, Seoung Won SHIN, Seung Schik YOO
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Patent number: 10504932Abstract: A display driver semiconductor device includes a high voltage well region being formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer. The first insulating layer may be formed using a chemical vapor deposition (CVD) process and the second insulating layer is formed using a thermal oxide process.Type: GrantFiled: November 30, 2017Date of Patent: December 10, 2019Assignee: MagnaChip Semiconductor, Ltd.Inventors: Bo Seok Oh, Hee Hwan Ji, Jeong Hyeon Park
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Publication number: 20190028098Abstract: A semiconductor device includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first gate insulator, a first source region and a first drain region, a pair of lightly doped drain (LDD) regions that are each shallower than the first source region and the first drain region, and a first gate electrode. The second transistor includes a second gate insulator, a second source region and a second drain region, a pair of drift regions that encompass the second source region and the second drain region respectively, and a second gate electrode, and the third transistor comprises a third gate insulator, a third source region and a third drain region, and a pair of drift regions that encompass the third source and the third drain regions respectively, and a third gate electrode. The second gate insulator is thinner than the other gate insulators.Type: ApplicationFiled: September 25, 2018Publication date: January 24, 2019Applicant: Magnachip Semiconductor, Ltd.Inventors: Jeong Hyeon PARK, Bo Seok OH, Hee Hwan JI
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Patent number: 10116305Abstract: A semiconductor device includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first gate insulator, a first source region and a first drain region, a pair of lightly doped drain (LDD) regions that are each shallower than the first source region and the first drain region, and a first gate electrode. The second transistor includes a second gate insulator, a second source region and a second drain region, a pair of drift regions that encompass the second source region and the second drain region respectively, and a second gate electrode, and the third transistor comprises a third gate insulator, a third source region and a third drain region, and a pair of drift regions that encompass the third source and the third drain regions respectively, and a third gate electrode. The second gate insulator is thinner than the other gate insulators.Type: GrantFiled: December 28, 2016Date of Patent: October 30, 2018Assignee: Magnachip Semiconductor, Ltd.Inventors: Jeong Hyeon Park, Bo Seok Oh, Hee Hwan Ji
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Publication number: 20180083043Abstract: A display driver semiconductor device includes a high voltage well region being formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer. The first insulating layer may be formed using a chemical vapor deposition (CVD) process and the second insulating layer is formed using a thermal oxide process.Type: ApplicationFiled: November 30, 2017Publication date: March 22, 2018Applicant: MagnaChip Semiconductor, Ltd.Inventors: Bo Seok OH, Hee Hwan JI, Jeong Hyeon PARK
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Publication number: 20180019262Abstract: A display driver semiconductor device includes a high voltage well region being formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer. The first insulating layer may be formed using a chemical vapor deposition (CVD) process and the second insulating layer is formed using a thermal oxide process.Type: ApplicationFiled: March 6, 2017Publication date: January 18, 2018Applicant: Magnachip Semiconductor, Ltd.Inventors: Bo Seok OH, Hee Hwan JI, Jeong Hyeon PARK
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Patent number: 9871063Abstract: A display driver semiconductor device includes a high voltage well region being formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer. The first insulating layer may be formed using a chemical vapor deposition (CVD) process and the second insulating layer is formed using a thermal oxide process.Type: GrantFiled: March 6, 2017Date of Patent: January 16, 2018Assignee: Magnachip Semiconductor, Ltd.Inventors: Bo Seok Oh, Hee Hwan Ji, Jeong Hyeon Park
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Publication number: 20180013421Abstract: A semiconductor device includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first gate insulator, a first source region and a first drain region, a pair of lightly doped drain (LDD) regions that are each shallower than the first source region and the first drain region, and a first gate electrode. The second transistor includes a second gate insulator, a second source region and a second drain region, a pair of drift regions that encompass the second source region and the second drain region respectively, and a second gate electrode, and the third transistor comprises a third gate insulator, a third source region and a third drain region, and a pair of drift regions that encompass the third source and the third drain regions respectively, and a third gate electrode. The second gate insulator is thinner than the other gate insulators.Type: ApplicationFiled: December 28, 2016Publication date: January 11, 2018Applicant: Magnachip Semiconductor, Ltd.Inventors: Jeong Hyeon PARK, Bo Seok OH, Hee Hwan JI
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Patent number: 8782902Abstract: A method of making a bearing includes providing a bearing intermediate, which is unfinished while having an overall shape of a finished bearing product; and repeatedly impacting a surface of the bearing intermediate at one or more ultrasonic frequencies to modify characteristics of the bearing intermediate. The resulting bearing intermediate or finished bearing product includes nano-size grains at or underneath the surface.Type: GrantFiled: October 13, 2009Date of Patent: July 22, 2014Assignee: Designmecha Co., Ltd.Inventors: Young Sik Pyun, Jeong Hyeon Park, Chang Sik Kim, In Ho Cho
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Publication number: 20100024218Abstract: A method of making a bearing includes providing a bearing intermediate, which is unfinished while having an overall shape of a finished bearing product; and repeatedly impacting a surface of the bearing intermediate at one or more ultrasonic frequencies to modify characteristics of the bearing intermediate. The resulting bearing intermediate or finished bearing product includes nano-size grains at or underneath the surface.Type: ApplicationFiled: October 13, 2009Publication date: February 4, 2010Applicant: DESIGNMECHA CO., LTD.Inventors: YOUNG SIK PYUN, JEONG HYEON PARK, CHANG SIK KIM, IN HO CHO