Abstract: Provided is a color image sensor including: a silicon semiconductor chip housed in a package and having a plurality of pixels; an optical glass formed on an upper portion of the silicon semiconductor chip and having a color filter pattern formed thereon; and a window glass formed on the optical glass. According to embodiments of the present invention, color interference between neighboring pixels can be minimized, and the size of the silicon semiconductor chip can be designed smaller under the same color separation condition, which is economical.

Abstract: A radiation-resistant image sensor package may include: a substrate; an image sensor disposed over the substrate; and an optical cover disposed over the image sensor, wherein a radiation-resistant passivation layer is coupled to the optical cover.

Abstract: A radiation-resistant image sensor package may include: a substrate; an image sensor disposed over the substrate; and an optical cover disposed over the image sensor, wherein a radiation-resistant passivation layer is coupled to the optical cover.

Abstract: A method of erasing a semiconductor memory device comprises grouping a plurality of word lines of each memory block into at least two groups based on intensity of disturbance between neighboring word lines; performing an erase operation by applying a ground voltage to all word lines of a selected memory block and by applying an erase voltage to a well of the selected memory block; and first increasing the ground voltage of one group of the groups to a positive voltage during the erase operation.

Abstract: A method of erasing a semiconductor memory device comprises grouping a plurality of word lines of each memory block into at least two groups based on intensity of disturbance between neighboring word lines; performing an erase operation by applying a ground voltage to all word lines of a selected memory block and by applying an erase voltage to a well of the selected memory block; and first increasing the ground voltage of one group of the groups to a positive voltage during the erase operation.

Abstract: A nonvolatile memory device and a manufacturing method thereof are provided. The nonvolatile memory device includes memory cells which are formed in a cell array region, peripheral circuit devices which are formed in a peripheral circuit region at the periphery of the cell array region, a field oxide film which is formed between the cell array region and the peripheral circuit region, and a dummy conductive pattern which is formed along and on the field oxide film. Accordingly, damage to the substrate formed between the peripheral circuit region and the cell array region can be reduced, thus a characteristic of insulation between devices can be enhanced.

Abstract: A nonvolatile memory device and a manufacturing method thereof are provided. The nonvolatile memory device includes memory cells which are formed in a cell array region, peripheral circuit devices which are formed in a peripheral circuit region at the periphery of the cell array region, a field oxide film which is formed between the cell array region and the peripheral circuit region, and a dummy conductive pattern which is formed along and on the field oxide film. Accordingly, damage to the substrate formed between the peripheral circuit region and the cell array region can be reduced, thus a characteristic of insulation between devices can be enhanced.

Abstract: A method for manufacturing a nonvolatile memory device having a memory cell array and a peripheral circuit portion which includes the steps of forming a field oxide film on a semiconductor substrate to form an active region and an isolation region; forming a first dielectric layer on the entire surface of the substrate where the field oxide film is formed; forming a first conductive layer on the dielectric layer; patterning the conductive layer to form a first conductive pattern in the memory cell array and in the peripheral circuit portion; forming a second dielectric layer on the entire surface of the substrate where the first conductive pattern is formed; selectively etching the second dielectric layer, first conductive pattern, and first dielectric layer formed in the peripheral circuit portion to expose the surface of the substrate in the peripheral circuit portion; forming a third dielectric layer on the substrate of the exposed peripheral circuit portion and on the second dielectric layer of the cell a

Abstract: An integrated circuit fuse circuit includes a plurality of fuses each connected to an output terminal, and a plurality of fuse programming circuits, a respective one of which is connected between a respective fuse and a reference voltage. Each of the fuse programming circuits includes a pair of complementary bipolar transistors and a field effect transistor. The pair of complementary bipolar transistors produce a large current through the associated fuse in response to a fuse programming signal which is applied to the field effect transistor. The fuse programming circuit may be fabricated in an integrated circuit by providing first and second spaced apart regions of second conductivity type in a well of first conductivity type, and a third region of the first conductivity type in the first region. An insulated gate is provided on the face between the first and second spaced apart regions. An insulated fuse is also provided on the face, electrically connected to the third region.