Abstract: An integrated circuit fuse circuit includes a plurality of fuses each connected to an output terminal, and a plurality of fuse programming circuits, a respective one of which is connected between a respective fuse and a reference voltage. Each of the fuse programming circuits includes a pair of complementary bipolar transistors and a field effect transistor. The pair of complementary bipolar transistors produce a large current through the associated fuse in response to a fuse programming signal which is applied to the field effect transistor. The fuse programming circuit may be fabricated in an integrated circuit by providing first and second spaced apart regions of second conductivity type in a well of first conductivity type, and a third region of the first conductivity type in the first region. An insulated gate is provided on the face between the first and second spaced apart regions. An insulated fuse is also provided on the face, electrically connected to the third region.

Abstract: An electrically erasable and programmable read only memory device includes a first select device and a NAND cell string consisting of a plurality or memory transistors. Each memory transistor has a floating gate separated by a tunnel oxide layer from a channel region formed on a semiconductor substrate and a control gate separated by an interlayer insulation layer from the floating gate. Respective channels of the memory transistors are serially connected to each other by source-drain regions. The control gate is connected to a corresponding word line. The first select device connects one terminal of the NAND cell string to a corresponding bit line. A resistor having a preset resistance value is connected between the first select device and a bit line. An amplifying device amplifies current flowing through the NAND cell string and supplies the amplified current to the bit line.

Abstract: The present invention discloses a non-volatile memory device having a multi-level gate structure. The storage cell transistor in the cell array region and the transistor in the peripheral circuit region have the same multi-level gate structure. Also, multi-level polycrystalline silicon layers in the peripheral circuit region are connected to each other, and thus utilized as an electrically singular gate electrode. The gate structures of the two regions are formed through a single etching process, so that the decreased processing number of photolithography simplifies overall process, and reduces the damage on the field oxide layer to thereby enhance an insulating performance.