Abstract: Provided is a ferroelectric-based synaptic device and a three-dimensional synaptic device stack using the same. The synaptic device includes a source, a drain, a semiconductor body in which a channel region are formed, a gate electrode, and an insulating layer stack disposed between the semiconductor body and the gate electrode. The insulating layer stack includes: a charge trap layer disposed on the channel region of the semiconductor body and is made of a material capable of storing or trapping electric charges; a ferroelectric layer made of a ferroelectric material; and an insulating layer disposed between the charge trap layer and the ferroelectric layer. The synaptic device is characterized in that weight information is volatilely stored in the charge trap layer and non-volatilely stored in the ferroelectric layer.

Abstract: Disclosed is an observation device for measuring an observation object while tracking the observation object by rotating an observation unit (10), wherein the observation device comprises a rotary unit (40) which includes: one end coupled to a support unit (20) through a first shaft rotating part (30) having a rotary shaft perpendicular to the side surface of the support unit (20); and the other end coupled to the observation unit (10) through a second shaft rotating part (50) having a rotary shaft perpendicular to the rotary shaft of the first shaft rotating part (30). Therefore, the observation device neither has a blind zone difficult to be observed nor requires rapid rotation of the rotary shaft, and thus can continuously observe objects ranging from a low-speed observation object, such as a celestial body or a planet, to a high-speed observation object, such as a satellite or a rocket.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, the memory system may receive a default enabled information from the host. The default enabled information indicates whether the host maintains a configuration of a host memory buffer in the host and target data stored in the host memory buffer when the memory system is in a low power mode state in which power supplied from the host is cut off.

Abstract: A memory controller includes a buffer, a prefetch controller, and a boot controller. The buffer stores workload information including a history of an expected I/O request expected to be received from a host during booting operation. The prefetch controller is configured to, before a target I/O request is received from the host after start of booting, read expected data corresponding to the expected I/O request from memory devices based on workload information, and store the expected data in the buffer. The boot controller updates the workload information based on the target I/O request depending on whether target data corresponding to the target I/O request is included in the expected data, and stores updated workload information in an area in which data is readable with a minimum number of accesses from a plurality of the memory devices.

Abstract: The present invention relates to a tracking device for tracking and observing or communicating with moving objects in space or in the atmosphere, wherein the present invention is devised to satisfy the aforementioned needs and an object of the present invention is to provide a tracking device of enabling a single mount to change a posture by one of an altitude-azimuth (ALT-AZ) control method, an equatorial control method, and an altitude-altitude (ALT-ALT) control method so as to facilitate the best tracking according to the operation characteristics of a moving object on the celestial sphere by variously controlling an installation angle of a main rotation shaft.

Abstract: A resist stripper composition according to an embodiment includes an alkali compound including an ammonium hydroxide-based compound, ethanol, and a polar organic solvent, which includes a sulfoxide-based compound. In a pattern formation method according to an embodiment, a photoresist pattern is formed on a substrate, a conductive pattern using the photoresist pattern is formed, and the photoresist pattern is removed by using the resist stripper composition. A resist stripper having an improved stripping rate and resist solubility is provided.

Abstract: A memory controller includes a buffer, a prefetch controller, and a boot controller. The buffer stores workload information including a history of an expected I/O request expected to be received from a host during booting operation. The prefetch controller is configured to, before a target I/O request is received from the host after start of booting, read expected data corresponding to the expected I/O request from memory devices based on workload information, and store the expected data in the buffer. The boot controller updates the workload information based on the target I/O request depending on whether target data corresponding to the target I/O request is included in the expected data, and stores updated workload information in an area in which data is readable with a minimum number of accesses from a plurality of the memory devices.

Abstract: The present invention relates to an observation apparatus which changes and moves planar position coordinates of a moving object connected to an observation unit, so as to adjust an observation direction of the observation unit and a change speed of the observation direction, such that objects moving at low to high speeds can be tracked and observed, and objects in the celestial direction can be observed.

Abstract: According to embodiments of the present disclosure, there may be provided a memory system and an operating method thereof, including a host accessible area accessible directly from an external device, transmitting information on the host accessible area to an external memory, receiving a direct memory access request generated based on the information for the host accessible area from the external device according to an urgent event, and providing the external device with a direct memory access to the host accessible area in response to the direct memory access request.

Abstract: A data processing system may include a storage device configured to: transmit, to an exterior, prediction information, for each power mode, that indicates a predicted time for performing a background operation for managing a memory device; and perform the background operation in an idle state of the storage device by switching to a corresponding power mode in response to a power mode control signal that is received in the idle state; and a control device configured to: determine a power mode of the storage device and an idle time for the idle state during which the background operation is performed based on the prediction information; transmit the power mode control signal to the storage device; and suspend, during the idle time, execution of a command processing request transmitted to the storage device.

Abstract: A host device includes a Host Memory Buffer (HMB) including a plurality of memory areas, each memory area configured to store data provided from a storage device which is in communication with the host device, and a host controller configured to generate reliability information of each of the plurality of memory areas, and in communication with the storage device to provide the reliability information to the storage device.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, the memory system may receive a default enabled information from the host. The default enabled information indicates whether the host maintains a configuration of a host memory buffer in the host and target data stored in the host memory buffer when the memory system is in a low power mode state in which power supplied from the host is cut off.

Abstract: A storage device of the present disclosure includes a memory device configured to store a plurality of address maps indicating a mapping relationship between a logical address and a physical address, and a memory controller configured to, when the storage device is in a power on state from a power off state, determine a priority rank of each of the plurality of address maps based on file attribute information received from a host and sequentially load the plurality of address maps according to the priority rank.

Abstract: A polypeptide having superoxide dismutase (SOD) activity and/or extracellular vesicles containing SOD is effective for the prevention and/or treatment of respiratory viral infection or diseases caused by respiratory viral infection in a subject. The polypeptide has SOD activity derived from a Bacillus amyloliquefaciens strain and/or extracellular vesicles containing SOD derived from a Bacillus subtillis strain is useful for the prevention and/or treatment of respiratory viral infection or diseases caused by respiratory viral infection in a subject.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, the memory system may receive a default enabled information from the host. The default enabled information indicates whether the host maintains a configuration of a host memory buffer in the host and target data stored in the host memory buffer when the memory system is in a low power mode state in which power supplied from the host is cut off.

Abstract: The present invention relates, in part, to methods of preventing or treating macular degeneration in a subject by co-administering a superoxide dismutase enzyme and probiotic Bacillus sp. spores, especially a Bacillus amyloliquefaciens GF423 or GF424 mutant strain. The present invention also provides pharmaceutical and/or food compositions comprising a superoxide dismutase enzyme and probiotic Bacillus sp. spores.

Abstract: A heat management circuit may include a throttling circuit configured to cool, for a predetermined time amount, at least one semiconductor functional circuit, which is designed to perform a predetermined function, when a plurality of first temperature signals respectively transmitted from a plurality of temperature sensors installed in the semiconductor functional circuit satisfy a throttling condition; and an analysis unit configured to receive, after lapse of the predetermined time amount, a plurality of second temperature signals from the respective temperature sensors, determine whether the cooling is successful or fails, and detect a temperature sensor having outputted a second temperature signal of abnormal value when the cooling is determined to fail.

Abstract: Provided is a ferroelectric-based synaptic device and a three-dimensional synaptic device stack using the same. The synaptic device includes a source, a drain, a semiconductor body in which a channel region are formed, a gate electrode, and an insulating layer stack disposed between the semiconductor body and the gate electrode. The insulating layer stack includes: a charge trap layer disposed on the channel region of the semiconductor body and is made of a material capable of storing or trapping electric charges; a ferroelectric layer made of a ferroelectric material; and an insulating layer disposed between the charge trap layer and the ferroelectric layer. The synaptic device is characterized in that weight information is volatilely stored in the charge trap layer and non-volatilely stored in the ferroelectric layer.

Abstract: A data processing system may include a storage device configured to: transmit, to an exterior, prediction information, for each power mode, that indicates a predicted time for performing a background operation for managing a memory device; and perform the background operation in an idle state of the storage device by switching to a corresponding power mode in response to a power mode control signal that is received in the idle state; and a control device configured to: determine a power mode of the storage device and an idle time for the idle state during which the background operation is performed based on the prediction information; transmit the power mode control signal to the storage device; and suspend, during the idle time, execution of a command processing request transmitted to the storage device.

Abstract: The present technology provides a method of operating a host communicating with a memory system including a journal area and a data area. The method of operating the host includes determining to update old data stored in the memory system, transferring, to the memory system, a write command for writing journal data and meta journal data for updating the old data to the journal area, and transferring, to the memory system, a write command for writing new data corresponding to the journal data to the data area in response to a write completion of the meta journal data and the journal data received from the memory system. Each of the meta journal data and the journal data includes a descriptor identifier (ID) indicating the same write transaction.