Abstract: Disclosed are novel compounds of Chemical Formula 1, optical isomers of the compounds, and pharmaceutically acceptable salts of the compounds or the optical isomers. The compounds, isomers, and salts exhibit excellent activity as GLP-1 receptor agonists. In particular, they, as GLP-1 receptor agonists, exhibit excellent glucose tolerance, thus having a great potential to be used as therapeutic agents for metabolic diseases. Moreover, they exhibit excellent pharmacological safety for cardiovascular systems.

Abstract: A semiconductor device capable of improving a device performance and a reliability is provided. The semiconductor device comprising a gate structure including a gate electrode on a substrate, a source/drain pattern on a side face of the gate electrode, on the substrate and, a source/drain contact connected to the source/drain pattern, on the source/drain pattern, a gate contact connected to the gate electrode, on the gate electrode, and a wiring structure connected to the source/drain contact and the gate contact, on the source/drain contact and the gate contact, wherein the wiring structure includes a first via plug, a second via plug, and a wiring line connected to the first via plug and the second via plug, the first via plug has a single conductive film structure, and the second via plug includes a lower via filling film, and an upper via filling film on the lower via filling film.

Abstract: Disclosed are a joining structure of different kinds of conductors, a joining method of different kinds of conductors, and a joint of power cables capable of improving joining reliability of a junction of the different kinds of conductors.

Abstract: A semiconductor device capable of improving a device performance and a reliability is provided. The semiconductor device comprising a gate structure including a gate electrode on a substrate, a source/drain pattern on a side face of the gate electrode, on the substrate and, a source/drain contact connected to the source/drain pattern, on the source/drain pattern, a gate contact connected to the gate electrode, on the gate electrode, and a wiring structure connected to the source/drain contact and the gate contact, on the source/drain contact and the gate contact, wherein the wiring structure includes a first via plug, a second via plug, and a wiring line connected to the first via plug and the second via plug, the first via plug has a single conductive film structure, and the second via plug includes a lower via filling film, and an upper via filling film on the lower via filling film.

Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.

Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device including a substrate; an insulating layer on the substrate, the insulating layer including a first trench and a second trench therein, the second trench having an aspect ratio that is smaller than an aspect ratio of the first trench; a barrier layer in the first trench and the second trench; a seed layer on the barrier layer in the first trench and the second trench; a first bulk layer on the seed layer and filled in the first trench; and a second bulk layer on the seed layer and filled in the second trench, wherein an average grain size of the second bulk layer is larger than an average grain size of the first bulk layer.

Abstract: A semiconductor device includes an active fin partially protruding from an isolation pattern on a substrate, a gate structure on the active fin, a source/drain layer on a portion of the active fin adjacent to the gate structure, a source/drain layer on a portion of the active fin adjacent to the gate structure, a metal silicide pattern on the source/drain layer, and a plug on the metal silicide pattern. The plug includes a second metal pattern, a metal nitride pattern contacting an upper surface of the metal silicide pattern and covering a bottom and a sidewall of the second metal pattern, and a first metal pattern on the metal silicide pattern, the first metal pattern covering an outer sidewall of the metal nitride pattern. A nitrogen concentration of the first metal pattern gradually decreases according to a distance from the outer sidewall of the metal nitride pattern.

Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.

Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device including a substrate; an insulating layer on the substrate, the insulating layer including a first trench and a second trench therein, the second trench having an aspect ratio that is smaller than an aspect ratio of the first trench; a barrier layer in the first trench and the second trench; a seed layer on the barrier layer in the first trench and the second trench; a first bulk layer on the seed layer and filled in the first trench; and a second bulk layer on the seed layer and filled in the second trench, wherein an average grain size of the second bulk layer is larger than an average grain size of the first bulk layer.

Abstract: Semiconductor devices may include a structure on a substrate, an insulating interlayer, a metal silicide pattern, a first barrier pattern, a second barrier pattern and a metal pattern. The structure may include silicon. The insulating interlayer may include a contact hole exposing a surface of the structure. The metal silicide pattern may be in a lower portion of the contact hole, and the metal silicide pattern may directly contact the exposed surface of the structure. The first barrier pattern may directly contact an upper surface of the metal silicide pattern and a sidewall of the contact hole. The first barrier pattern may include a metal nitride. The second barrier pattern may be formed on the first barrier pattern. The second barrier pattern may include a metal nitride. The metal pattern may be formed on the second barrier pattern. The metal pattern may be in the contact hole.

Abstract: A semiconductor device includes an active fin partially protruding from an isolation pattern on a substrate, a gate structure on the active fin, a source/drain layer on a portion of the active fin adjacent to the gate structure, a source/drain layer on a portion of the active fin adjacent to the gate structure, a metal silicide pattern on the source/drain layer, and a plug on the metal silicide pattern. The plug includes a second metal pattern, a metal nitride pattern contacting an upper surface of the metal silicide pattern and covering a bottom and a sidewall of the second metal pattern, and a first metal pattern on the metal silicide pattern, the first metal pattern covering an outer sidewall of the metal nitride pattern. A nitrogen concentration of the first metal pattern gradually decreases according to a distance from the outer sidewall of the metal nitride pattern.

Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.

Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.

Abstract: An electrical transmission line for transmitting electricity is made of a composite material in which aluminum and a plurality of carbon nanotubes are combined, and a weight ratio of the carbon nanotubes to the aluminum is 0.5 to 3 wt %. The carbon nanotubes are oriented at an angle within 30° along a length direction of the electrical transmission line.

Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.

Abstract: An electrical transmission line for transmitting electricity is made of a composite material in which aluminum and a plurality of carbon nanotubes are combined, and a weight ratio of the carbon nanotubes to the aluminum is 0.5 to 3 wt %. The carbon nanotubes are oriented at an angle within 30° along a length direction of the electrical transmission line.

Abstract: A method for manufacturing a very low roughness copper foil and an apparatus for manufacturing the copper foil. In the method of the present invention, a pickling process, an electrolytic polishing process and a washing process are successively performed after the copper foil was manufactured. In order to manufacture the very low roughness copper foil, the electrolytic polishing process is accomplished with the copper foil to face a metal cathode plate and supplying a current in order to perform the electrolytic polishing.

Abstract: A method for manufacturing a very low roughness copper foil and an apparatus for manufacturing the copper foil. In the method of the present invention, a pickling process, an electrolytic polishing process and a washing process are successively performed after the copper foil was manufactured. In order to manufacture the very low roughness copper foil, the electrolytic polishing process is accomplished with the copper foil to face a metal cathode plate and supplying a current in order to perform the electrolytic polishing.

Abstract: The present invention relates to a method for manufacturing a low roughness electrodeposited copper foil, and an electrodeposited copper foil manufactured thereby, and uses an electrolyte which basically consists of a sulfuric acid, a copper ion and a chloride ion is adapted with an additive which consists of a HEC (Hydroxyethyl Cellulose) of 0.05˜50 ppm, a SPS (bis(sodiumsulfopropyl)disulfide) of 0.05˜20 ppm, and a gelatin of 0.1˜100 ppm. The present invention is adapted to manufacture a low roughness electrodeposited copper foil using a conventional copper foil manufacture facility and the electrodeposited copper foil according to the present invention is adapted as a material for a copper clad laminate for a printed circuit substrate and an electrode material for a lithium ion battery.