Abstract: This disclosure relates to image sensors and electronic apparatuses including the same. An image sensor including: a pixel area including shared pixels, wherein each of the shared pixels includes at least two photodiodes that form a group and share a floating diffusion (FD) area; and a transistor (TR) area adjacent to the pixel area, wherein the TR area includes transistor sets corresponding to the shared pixels, wherein, when a first shared pixel and a second shared pixel are arranged adjacent to each other in a first direction, a first TR set corresponding to the first shared pixel and a second TR set corresponding to the second shared pixel share a source region of a first selection TR.

Abstract: An image sensor includes a substrate with a first surface opposite a second surface, a pixel isolation pattern defining first and second unit pixels adjacent to each other in the substrate, and first and second separation patterns in the substrate. The first unit pixel includes first and second photoelectric conversion parts along a first direction. The second unit pixel includes third and fourth photoelectric conversion parts along a second direction intersecting the first direction. The first separation pattern extends in the second direction between the first and second photoelectric conversion parts. The second separation pattern extends in the first direction between the third and fourth photoelectric conversion parts. A width of the pixel isolation pattern, a width of the first separation pattern, and a width of the second separation pattern each decrease from the second surface of the substrate toward the first surface of the substrate.

Abstract: This disclosure relates to image sensors and electronic apparatuses including the same. An image sensor including: a pixel area including shared pixels, wherein each of the shared pixels includes at least two photodiodes that form a group and share a floating diffusion (FD) area; and a transistor (TR) area adjacent to the pixel area, wherein the TR area includes transistor sets corresponding to the shared pixels, wherein, when a first shared pixel and a second shared pixel are arranged adjacent to each other in a first direction, a first TR set corresponding to the first shared pixel and a second TR set corresponding to the second shared pixel share a source region of a first selection TR.

Abstract: This disclosure relates to image sensors and electronic apparatuses including the same. An image sensor including: a pixel area including shared pixels, wherein each of the shared pixels includes at least two photodiodes that form a group and share a floating diffusion (FD) area; and a transistor (TR) area adjacent to the pixel area, wherein the TR area includes transistor sets corresponding to the shared pixels, wherein, when a first shared pixel and a second shared pixel are arranged adjacent to each other in a first direction, a first TR set corresponding to the first shared pixel and a second TR set corresponding to the second shared pixel share a source region of a first selection TR.

Abstract: This disclosure relates to image sensors and electronic apparatuses including the same. An image sensor including: a pixel area including shared pixels, wherein each of the shared pixels includes at least two photodiodes that form a group and share a floating diffusion (FD) area; and a transistor (TR) area adjacent to the pixel area, wherein the TR area includes transistor sets corresponding to the shared pixels, wherein, when a first shared pixel and a second shared pixel are arranged adjacent to each other in a first direction, a first TR set corresponding to the first shared pixel and a second TR set corresponding to the second shared pixel share a source region of a first selection TR.

Abstract: This disclosure relates to image sensors and electronic apparatuses including the same. An image sensor including: a pixel area including shared pixels, wherein each of the shared pixels includes at least two photodiodes that form a group and share a floating diffusion (FD) area; and a transistor (TR) area adjacent to the pixel area, wherein the TR area includes transistor sets corresponding to the shared pixels, wherein, when a first shared pixel and a second shared pixel are arranged adjacent to each other in a first direction, a first TR set corresponding to the first shared pixel and a second TR set corresponding to the second shared pixel share a source region of a first selection TR.

Abstract: This disclosure relates to image sensors and electronic apparatuses including the same. An image sensor including: a pixel area including shared pixels, wherein each of the shared pixels includes at least two photodiodes that form a group and share a floating diffusion (FD) area; and a transistor (TR) area adjacent to the pixel area, wherein the TR area includes transistor sets corresponding to the shared pixels, wherein, when a first shared pixel and a second shared pixel are arranged adjacent to each other in a first direction, a first TR set corresponding to the first shared pixel and a second TR set corresponding to the second shared pixel share a source region of a first selection TR.

Abstract: This disclosure relates to image sensors and electronic apparatuses including the same. An image sensor including: a pixel area including shared pixels, wherein each of the shared pixels includes at least two photodiodes that form a group and share a floating diffusion (FD) area; and a transistor (TR) area adjacent to the pixel area, wherein the TR area includes transistor sets corresponding to the shared pixels, wherein, when a first shared pixel and a second shared pixel are arranged adjacent to each other in a first direction, a first TR set corresponding to the first shared pixel and a second TR set corresponding to the second shared pixel share a source region of a first selection TR.

Abstract: This disclosure relates to image sensors and electronic apparatuses including the same. An image sensor including: a pixel area including shared pixels, wherein each of the shared pixels includes at least two photodiodes that form a group and share a floating diffusion (FD) area; and a transistor (TR) area adjacent to the pixel area, wherein the TR area includes transistor sets corresponding to the shared pixels, wherein, when a first shared pixel and a second shared pixel are arranged adjacent to each other in a first direction, a first TR set corresponding to the first shared pixel and a second TR set corresponding to the second shared pixel share a source region of a first selection TR.

Abstract: A power management system for semiconductor manufacturing prevents malfunctions of loading devices when transient power interruption occurs by maintaining power to the facilities for a period of time after the transient power interruption occurs. The system includes an emergency cutoff circuit, a first power controller, and a second power controller. The emergency cutoff circuit prevents trips in a power relay for one second at the time of transient power interruption. The first power controller discharges a DC voltage for a predetermined time period when AC power is not supplied through a power supply line thereto due to transient power interruption. The second power controller receives the DC voltage provided from the first power controller and discharges the DC voltage during a transient power interruption.

Abstract: A power management system for semiconductor manufacturing prevents malfunctions of loading devices when transient power interruption occurs by maintaining power to the facilities for a period of time after the transient power interruption occurs. The system includes an emergency cutoff circuit, a first power controller, and a second power controller. The emergency cutoff circuit prevents trips in a power relay for one second at the time of transient power interruption. The first power controller discharges a DC voltage for a predetermined time period when AC power is not supplied through a power supply line thereto due to transient power interruption. The second power controller receives the DC voltage provided from the first power controller and discharges the DC voltage during a transient power interruption.